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Hsinchu City, Taiwan
負責 高速 PLL 以及 Serdes 相關類比電路開發。 設計PCIe/USB/SATA相關APHY serdes電路，例如：USB4、PCIe5、25G serdes
2.5M ~ 4.5M TWD / year
3 years of experience required
No management responsibility
工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
PCIe/USB/MIPI-CSI/Display Port 相關之高速介面ditigal PHY IC設計
35K ~ 200K TWD / month
1 years of experience required
No management responsibility
