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RTL Project
RTL Project
Student
・
Taiwan
RTL Project
Simple MIPS CPU (without pipeline)
Block Diagram
Features
MCU based on RISC-V ISA (with pipeline)
Block Diagram
Feature
Simple Image Processing and Display Controller
Block Diagram
Features
IoT Data Filtering
Block Diagram
Features
My experience in digital circuit design.
This shows that I am familiar with digital circuit design, including the use of EDA tools (vcs, nWave, Primetime, Innovus, etc.).
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