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AI工程師、機器學習工程師、深度學習工程師、影像演算法工程師、資料科學家、Ai Application Engineer,Machine Learning Engineer,Deep Learning Engineer,Data Scientist
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Advanced Semiconductor Engineering, INC. 日月光半導體製造股份有限公司
U&U ENGINEERING INC均利科技股份有限公司
WPG Holdings Limited 大聯大投資控股(股)公司
亦思科技股份有限公司IS-Land Systems INC
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Available for paid companies
智慧製造全端開發工程師 @聯華電子股份有限公司
・
2022 ~ Present
AI工程師、機器學習工程師、深度學習工程師、影像演算法工程師、資料科學家、Ai Application Engineer,Machine Learning Engineer,Deep Learning Engineer,Data Scientist
Within one month
Python
Qt
Git
Employed
・
Ready to interview
Full-time / Interested in working remotely
4-6 years
元智大學 Yuan Ze University
・
工業工程與管理學系所
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Past
軟體開發高級工程師 @華友聯集團
・
2019 ~ 2023
軟體工程師
Within one month
React
Redux
.NET MVC
Unemployed
・
Ready to interview
Full-time / Interested in working remotely
6-10 years
國立雲林科技大學（NYUST）
・
資訊管理所
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ERP資訊工程師-ERP Software Engineer @南茂科技股份有限公司 ChipMOS TECHNOLOGIES
・
2022 ~ Present
Engineer, SA, SD, Data Analyst, PM
Within one month
C#
Java
WebMethods
Employed
・
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6-10 years
國立成功大學 National Cheng Kung University
・
Industrial and Information Management
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Offline
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Hsieh Azure
Past
R&D process integration engineer @ UMC
・
2014 ~ 2022
Semiconductor Engineer
More than one year
謝宗殷 (Azure) R&D technical manager Tainan City, Taiwan Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University. As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience. Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement. Email : azure[email protected] Phone:Work experience R&D technical manager • UMC JuneMarchnm FiNFET BEoL process development, product yield improvement and
Excel
reliability
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National Yang Ming Chiao Tung University
・
Electrical Engineering & IC design
50+
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Ling-Yu-Chien
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2021 ~ Present
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電影系

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Problem-Solving
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Adaptability
Ability to navigate unexpected situations; and keep up with shifting priorities, projects, clients, and technology.
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More than one year
Avatar of Hsieh Azure.
Hsieh Azure
R&D process integration engineer
Logo of UMC.
UMC
・
2014 ~ 2022
Tainan, 台灣
Professional Background
Current status
Unemployed
Job Search Progress
Not open to opportunities
Professions
Electronics Engineer, Process Engineer, I&C Engineer
Fields of Employment
Electronics / Telecommunications, Nanotechnology, Semiconductor
Work experience
10-15 years
Management
None
Skills
Excel
reliability
Process Integration
Yield Enhancement
Failure Analysis
Languages
English
・
Intermediate
Japanese
・
Beginner
Job search preferences
Positions
Semiconductor Engineer
Job types
Full-time
Locations
Tainan, Taiwan, Kaohsiung City, 台灣
Remote
Interested in working remotely
Freelance
No
Educations
School
National Yang Ming Chiao Tung University
Major
Electrical Engineering & IC design
Print

謝宗殷 (Azure)

R&D technical manager

  Tainan City, Taiwan

Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement.
Email : [email protected]
Phone: 0910-828-616

 

Work experience

R&D technical manager  •   UMC

June 2014 - March 2022

14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process development, yield ramp up and reliability improve. EM life time reaches 10,000 years at the 1000ppm specified customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process development, includes rules and test key design
3. 22nm eHV (device operating in 8V-27V) interconnect process development

Process integration engineer  •  Taiwan Semiconductor Manufacturing Company(TSMC)

July 2010 - April 2014

Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies
1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart)
2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development

Education

2006 - 2009

National Yang Ming Chiao Tung University

Electrical Engineering & IC design

2002 - 2006

Chang Gung University，CGU

Electrical Engineering Department

Personal advantage

  • Strong learning ability
  • Good at teamwork
  • High problem solving ability

Skills

  • Reliability improvement
  • Defect reduction
  • Process Integration
  • Yield Enhancement
  • Failure Analysis

Language

  • English — Intermediate

    Japanese — Elementary

Resume
Profile
Print

謝宗殷 (Azure)

R&D technical manager

  Tainan City, Taiwan

Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement.
Email : [email protected]
Phone: 0910-828-616

 

Work experience

R&D technical manager  •   UMC

June 2014 - March 2022

14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process development, yield ramp up and reliability improve. EM life time reaches 10,000 years at the 1000ppm specified customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process development, includes rules and test key design
3. 22nm eHV (device operating in 8V-27V) interconnect process development

Process integration engineer  •  Taiwan Semiconductor Manufacturing Company(TSMC)

July 2010 - April 2014

Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies
1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart)
2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development

Education

2006 - 2009

National Yang Ming Chiao Tung University

Electrical Engineering & IC design

2002 - 2006

Chang Gung University，CGU

Electrical Engineering Department

Personal advantage

  • Strong learning ability
  • Good at teamwork
  • High problem solving ability

Skills

  • Reliability improvement
  • Defect reduction
  • Process Integration
  • Yield Enhancement
  • Failure Analysis

Language

  • English — Intermediate

    Japanese — Elementary