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QA engineer @Innova Solutions Taiwan
2022 ~ Present
前端工程師 Front-End Developer
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Software Testing
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QA Plan and Strategy
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6-10 years
National United University
Information Management
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National Chung Cheng University
Management Information Systems
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R&D process integration engineer @ UMC
2014 ~ 2022
Semiconductor Engineer
More than one year
TSMC) JulyApril 2014 Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies 1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart) 2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development EducationNational Yang Ming Chiao Tung University Electrical Engineering & IC designChang Gung University,CGU Electrical Engineering Department Personal advantage Strong learning ability Good at teamwork High problem solving ability Skills Reliability improvement Defect reduction Process Integration Yield Enhancement Failure Analysis Language English — Intermediate Japanese — Elementary
Excel
reliability
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10-15 years
National Yang Ming Chiao Tung University
Electrical Engineering & IC design
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software Photoshop, Illustrator, Sketch, Zeplin 善於使用Photoshop, Illustrator, Sketch, Zeplin ░ Illustration/ hand-drawing with Graphic design experience 有 插圖/手繪與平面設計經驗 ░ Establish design guidelines 懂得建立設計規範 ░ Favorite in teamwork 喜歡團隊合作 contact me anytime LOCKER Pick system Transit - Passenger Feedback website Condo Key collections booking system Zoo Park / Incident Management System Red Cross Volunteer Registration Doodle Maru Doodle rope skipping Doodle A set of 40 digital stickers for LINE App Doodle have a
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Zeplin
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4-6 years
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Coordinator for Planning Department @CR Classification Society Kaohsiung Branch
2017 ~ Present
Coordinator for Planning Department
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Word
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6-10 years
National Tsing Hua University
Foreign Languages and Literature
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Chief Data Officer @Welhunt
2020 ~ Present
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manage a data team of 10 from scratch, responsible for forming strategic data transforming plan for company. 2.Build and design data center for data storage and integration data from different sources. 3.Design team KPI directly with CEO to motivate and quantify the contribution of teamwork. 4.Customize personal growing path for each member and build a sharing and life-long learning team culture. 5.Collaborate with PM and vendor to design the ERP system in order to accelerate operation efficiency. 6.Design and develop automation platform for multiple
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National Cheng Kung University
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接案室內設計師 @sysistudio
2015 ~ Present
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聯繫 | 企劃文案室內設計師 台中某建築事務所-台北分公司 ◆ 台灣台中 伯達行旅設計規劃案 http://www.hotelboda.com/index.php Teamwok 處理大廳設計|規劃室內居住空間 ◆ 中國深圳 中山翠亨蘭溪谷建案-樣板房規劃案 Teamwok 設計不同風格之樣板房 建材設定
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樹德科技大學 Shu-Te University
interior design

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More than one year
R&D process integration engineer
Logo of  UMC.
UMC
2014 ~ 2022
Tainan, 台灣
Professional Background
Current status
Unemployed
Job Search Progress
Not open to opportunities
Professions
Electronics Engineer, Process Engineer, I&C Engineer
Fields of Employment
Electronics / Telecommunications, Nanotechnology, Semiconductor
Work experience
10-15 years
Management
None
Skills
Excel
reliability
Process Integration
Yield Enhancement
Failure Analysis
Languages
English
Intermediate
Japanese
Beginner
Job search preferences
Positions
Semiconductor Engineer
Job types
Full-time
Locations
Tainan, Taiwan, Kaohsiung City, 台灣
Remote
Interested in working remotely
Freelance
No
Educations
School
National Yang Ming Chiao Tung University
Major
Electrical Engineering & IC design
Print

謝宗殷 (Azure)

R&D technical manager

  Tainan City, Taiwan

Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement.
Email : [email protected]
Phone: 0910-828-616

 

Work experience

R&D technical manager  •   UMC

June 2014 - March 2022

14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process development, yield ramp up and reliability improve. EM life time reaches 10,000 years at the 1000ppm specified customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process development, includes rules and test key design
3. 22nm eHV (device operating in 8V-27V) interconnect process development

Process integration engineer  •  Taiwan Semiconductor Manufacturing Company(TSMC)

July 2010 - April 2014

Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies
1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart)
2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development

Education

2006 - 2009

National Yang Ming Chiao Tung University

Electrical Engineering & IC design

2002 - 2006

Chang Gung University,CGU

Electrical Engineering Department

Personal advantage


  • Strong learning ability
  • Good at teamwork
  • High problem solving ability

Skills


  • Reliability improvement
  • Defect reduction
  • Process Integration
  • Yield Enhancement
  • Failure Analysis

Language


  • English — Intermediate

    Japanese — Elementary

Resume
Profile

謝宗殷 (Azure)

R&D technical manager

  Tainan City, Taiwan

Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement.
Email : [email protected]
Phone: 0910-828-616

 

Work experience

R&D technical manager  •   UMC

June 2014 - March 2022

14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process development, yield ramp up and reliability improve. EM life time reaches 10,000 years at the 1000ppm specified customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process development, includes rules and test key design
3. 22nm eHV (device operating in 8V-27V) interconnect process development

Process integration engineer  •  Taiwan Semiconductor Manufacturing Company(TSMC)

July 2010 - April 2014

Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies
1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart)
2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development

Education

2006 - 2009

National Yang Ming Chiao Tung University

Electrical Engineering & IC design

2002 - 2006

Chang Gung University,CGU

Electrical Engineering Department

Personal advantage


  • Strong learning ability
  • Good at teamwork
  • High problem solving ability

Skills


  • Reliability improvement
  • Defect reduction
  • Process Integration
  • Yield Enhancement
  • Failure Analysis

Language


  • English — Intermediate

    Japanese — Elementary