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No está abierto a oportunidades
Hsinchu City, Taiwan
Taiwan
台灣
新竹市, 台灣
Engineering
Tecnología
Menos de 1 año
1-2 años
2-4 años
De 4 a 6 años
6-10 años
10-15 años
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National Yang Ming Chiao Tung University
國立陽明交通大學
Taiwan
台灣
A tiempo completo
ASIC
Physical Design
System On A Chip
VLSI CAD
VLSI Design
No
En seis meses
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Master of Science (MS)
Master
2013
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GUC
TSMC
Interesado en trabajar a distancia
No freelance
Chinese - Nativo o bilingüe
English - Fluido
English
De 4 a 6 años
6-10 años
10-15 años
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Avatar of Kuan-Ting Chen.
Fuera de línea
Avatar of Kuan-Ting Chen.
Fuera de línea
Kuan-Ting Chen
Principal Engineer @TSMC
・
2021 ~ Presente
En seis meses
Kuan-Ting Chen Physical design engineer with 10 years of experience working in the semiconductors industry. Skilled in cell-based ASIC/SoC implementation and power integrity (EM/IR) analysis methodology, especially for advanced nodes (7/6/5/4/3nm). Familiar with Tcl/Perl scripting and design automation. Coordinate technical support and customer engagement with close collaboration with EDA vendors. Organize technological education to partners/customers. Fluent in Mandarin and English (TOEFL: 105/120). [email protected], Taiwan Engineering Skills PHYSICAL DESIGN
Physical Design
ASIC
System On A Chip
Empleado
・
No está abierto a oportunidades
A tiempo completo / Interesado en trabajar a distancia
6-10 años
National Chiao Tung University
・
Electronics Engineering
100+

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En seis meses
Avatar of Kuan-Ting Chen.
Kuan-Ting Chen
Principal Engineer @ TSMC
TSMC
・
2021 ~ Presente
Hsinchu, 新竹市台灣
Professional Background
Situación actual
Empleado
Progreso en la búsqueda de empleo
No está abierto a oportunidades
Professions
Other
Fields of Employment
Semiconductores
Experiencia laboral
6-10 años
Management
Ninguno
Habilidades
Physical Design
ASIC
System On A Chip
VLSI CAD
VLSI design
Idiomas
Chinese
・
Nativo o bilingüe
English
・
Fluido
Job search preferences
Posición
Tipo de trabajo
A tiempo completo
Ubicación
Taiwan, 台灣
A distancia
Interesado en trabajar a distancia
Freelance
No.
Educación
Escuela
National Chiao Tung University
Mayor
Electronics Engineering
Imprimir

Kuan-Ting Chen

Physical design engineer with 10 years of experience working in the semiconductors industry. Skilled in cell-based ASIC/SoC implementation and power integrity (EM/IR) analysis methodology, especially for advanced nodes (7/6/5/4/3nm). Familiar with Tcl/Perl scripting and design automation. Coordinate technical support and customer engagement with close collaboration with EDA vendors. Organize technological education to partners/customers. Fluent in Mandarin and English (TOEFL: 105/120).

[email protected]
+886-921672917
Hsinchu, Taiwan

Engineering Skills

PHYSICAL DESIGN
  • Establish and deploy physical design methodology in advanced nodes (7/6/5/4/3nm)
  • Design implementation from netlist to tape-out and PPA assessment in 7/6/5/4/3nm technologies
  • Proven knowledge of Cadence Innovus and Synopsys ICC2/FusionCompiler backend design flow
  • Familiar with Ansys Redhawk/Redhawk-CPA EM/IR methodology
CUSTOMER ENGAGEMENT, SUPPORT, and EDUCATION
  • Coordinate technical support to customers in the above areas of profession
  • Proactive and close collaboration with EDA vendors
  • Conduct technological training courses and technical application notes for partners/customers

Education

NATIONAL CHIAO TUNG UNIVERSITY, 2011 - 2013

M. Sc. of Electronics Engineering

NATIONAL CHIAO TUNG UNIVERSITY, 2007 - 2011

B.S. of Electronics Engineering

Professional Experience

INTEL CORPORATION, 2022 - Present

Physical Design Engineer, Design Service Engineering


  • 3DIC testchip execution
  • Heterogeneous integration flow enablement

TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD., 2019 - 2022

Principal Eningeer, Design Technology Platform


  • 6nm HPC segment customer engagement, flow pipeclean, and project on-site field support
  • 5/4/3nm HPC segment customer engagement, PPA assessment, and technical support
  • 5/4/3nm node EDA enablement and certification program
  • 20+ physical implementation flow trainings to customers in 7/6/5/3 nm technologies

GLOBAL UNICHIP CORPORATION, 2013 - 2019

Deputy Technical Manager, Design Service


  • 7nm HPC peripheral block implementation (2M inst.; P&R, timing closure, DRC/LVS)
  • 7nm GPU block implementation (1M inst.; P&R, path-finding, customer field support)
  • 7nm physical design flow and DDR IP hardening (P&R, timing closure, DRC/LVS, field support)
  • 5+ power integrity analysis projects in 28/16nm technology
  • 20+ APR and/or power integrity project support experience in sub-28nm nodes

Resume
Perfil
Imprimir

Kuan-Ting Chen

Physical design engineer with 10 years of experience working in the semiconductors industry. Skilled in cell-based ASIC/SoC implementation and power integrity (EM/IR) analysis methodology, especially for advanced nodes (7/6/5/4/3nm). Familiar with Tcl/Perl scripting and design automation. Coordinate technical support and customer engagement with close collaboration with EDA vendors. Organize technological education to partners/customers. Fluent in Mandarin and English (TOEFL: 105/120).

[email protected]
+886-921672917
Hsinchu, Taiwan

Engineering Skills

PHYSICAL DESIGN
  • Establish and deploy physical design methodology in advanced nodes (7/6/5/4/3nm)
  • Design implementation from netlist to tape-out and PPA assessment in 7/6/5/4/3nm technologies
  • Proven knowledge of Cadence Innovus and Synopsys ICC2/FusionCompiler backend design flow
  • Familiar with Ansys Redhawk/Redhawk-CPA EM/IR methodology
CUSTOMER ENGAGEMENT, SUPPORT, and EDUCATION
  • Coordinate technical support to customers in the above areas of profession
  • Proactive and close collaboration with EDA vendors
  • Conduct technological training courses and technical application notes for partners/customers

Education

NATIONAL CHIAO TUNG UNIVERSITY, 2011 - 2013

M. Sc. of Electronics Engineering

NATIONAL CHIAO TUNG UNIVERSITY, 2007 - 2011

B.S. of Electronics Engineering

Professional Experience

INTEL CORPORATION, 2022 - Present

Physical Design Engineer, Design Service Engineering


  • 3DIC testchip execution
  • Heterogeneous integration flow enablement

TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD., 2019 - 2022

Principal Eningeer, Design Technology Platform


  • 6nm HPC segment customer engagement, flow pipeclean, and project on-site field support
  • 5/4/3nm HPC segment customer engagement, PPA assessment, and technical support
  • 5/4/3nm node EDA enablement and certification program
  • 20+ physical implementation flow trainings to customers in 7/6/5/3 nm technologies

GLOBAL UNICHIP CORPORATION, 2013 - 2019

Deputy Technical Manager, Design Service


  • 7nm HPC peripheral block implementation (2M inst.; P&R, timing closure, DRC/LVS)
  • 7nm GPU block implementation (1M inst.; P&R, path-finding, customer field support)
  • 7nm physical design flow and DDR IP hardening (P&R, timing closure, DRC/LVS, field support)
  • 5+ power integrity analysis projects in 28/16nm technology
  • 20+ APR and/or power integrity project support experience in sub-28nm nodes