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上級
On
就職を希望していません
Hsinchu City, Taiwan
Taiwan
台灣
新竹市, 台灣
Engineering
技術
1年未満
1〜2年
2〜4年
4〜6年
6〜10年
10〜15年
15年以上
AI Smart Matching
On
National Yang Ming Chiao Tung University
國立陽明交通大學
Taiwan
台灣
フルタイム
ASIC
Physical Design
System On A Chip
VLSI CAD
VLSI design
No
6ヶ月以内
条件に合うものが見つかりませんでした。
Master of Science (MS)
Master
2013
Current company
Off
Select all
GUC
TSMC
リモートワークに興味あり
非フリーランス
Chinese - ネイティブまたはバイリンガル
English - 流暢
English
4〜6年
6〜10年
10〜15年
15年以上
  • 既読の検索結果を除く
  • Show all experiences
Avatar of Kuan-Ting Chen.
オフライン
Avatar of Kuan-Ting Chen.
オフライン
Kuan-Ting Chen
Principal Engineer @TSMC
・
2021 ~ 現在
6ヶ月以内
Kuan-Ting Chen Physical design engineer with 10 years of experience working in the semiconductors industry. Skilled in cell-based ASIC/SoC implementation and power integrity (EM/IR) analysis methodology, especially for advanced nodes (7/6/5/4/3nm). Familiar with Tcl/Perl scripting and design automation. Coordinate technical support and customer engagement with close collaboration with EDA vendors. Organize technological education to partners/customers. Fluent in Mandarin and English (TOEFL: 105/120). [email protected], Taiwan Engineering Skills PHYSICAL DESIGN
Physical Design
ASIC
System On A Chip
就職中
・
就職を希望していません
フルタイム / リモートワークに興味あり
6〜10年
National Chiao Tung University
・
Electronics Engineering
100+

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6ヶ月以内
Avatar of Kuan-Ting Chen.
Kuan-Ting Chen
Principal Engineer @ TSMC
TSMC
・
2021 ~ 現在
Hsinchu, 新竹市台灣
Professional Background
現在の状況
就職中
求人検索の進捗
就職を希望していません
Professions
Other
Fields of Employment
半導体
職務経験
6〜10年
Management
なし
スキル
Physical Design
ASIC
System On A Chip
VLSI CAD
VLSI design
言語
Chinese
・
ネイティブまたはバイリンガル
English
・
流暢
Job search preferences
希望のポジション
求人タイプ
フルタイム
希望の勤務地
Taiwan, 台灣
リモートワーク
リモートワークに興味あり
Freelance
いいえ。
学歴
学校
National Chiao Tung University
専攻
Electronics Engineering
印刷

Kuan-Ting Chen

Physical design engineer with 10 years of experience working in the semiconductors industry. Skilled in cell-based ASIC/SoC implementation and power integrity (EM/IR) analysis methodology, especially for advanced nodes (7/6/5/4/3nm). Familiar with Tcl/Perl scripting and design automation. Coordinate technical support and customer engagement with close collaboration with EDA vendors. Organize technological education to partners/customers. Fluent in Mandarin and English (TOEFL: 105/120).

[email protected]
+886-921672917
Hsinchu, Taiwan

Engineering Skills

PHYSICAL DESIGN
  • Establish and deploy physical design methodology in advanced nodes (7/6/5/4/3nm)
  • Design implementation from netlist to tape-out and PPA assessment in 7/6/5/4/3nm technologies
  • Proven knowledge of Cadence Innovus and Synopsys ICC2/FusionCompiler backend design flow
  • Familiar with Ansys Redhawk/Redhawk-CPA EM/IR methodology
CUSTOMER ENGAGEMENT, SUPPORT, and EDUCATION
  • Coordinate technical support to customers in the above areas of profession
  • Proactive and close collaboration with EDA vendors
  • Conduct technological training courses and technical application notes for partners/customers

Education

NATIONAL CHIAO TUNG UNIVERSITY, 2011 - 2013

M. Sc. of Electronics Engineering

NATIONAL CHIAO TUNG UNIVERSITY, 2007 - 2011

B.S. of Electronics Engineering

Professional Experience

INTEL CORPORATION, 2022 - Present

Physical Design Engineer, Design Service Engineering


  • 3DIC testchip execution
  • Heterogeneous integration flow enablement

TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD., 2019 - 2022

Principal Eningeer, Design Technology Platform


  • 6nm HPC segment customer engagement, flow pipeclean, and project on-site field support
  • 5/4/3nm HPC segment customer engagement, PPA assessment, and technical support
  • 5/4/3nm node EDA enablement and certification program
  • 20+ physical implementation flow trainings to customers in 7/6/5/3 nm technologies

GLOBAL UNICHIP CORPORATION, 2013 - 2019

Deputy Technical Manager, Design Service


  • 7nm HPC peripheral block implementation (2M inst.; P&R, timing closure, DRC/LVS)
  • 7nm GPU block implementation (1M inst.; P&R, path-finding, customer field support)
  • 7nm physical design flow and DDR IP hardening (P&R, timing closure, DRC/LVS, field support)
  • 5+ power integrity analysis projects in 28/16nm technology
  • 20+ APR and/or power integrity project support experience in sub-28nm nodes

Resume
プロフィール
印刷

Kuan-Ting Chen

Physical design engineer with 10 years of experience working in the semiconductors industry. Skilled in cell-based ASIC/SoC implementation and power integrity (EM/IR) analysis methodology, especially for advanced nodes (7/6/5/4/3nm). Familiar with Tcl/Perl scripting and design automation. Coordinate technical support and customer engagement with close collaboration with EDA vendors. Organize technological education to partners/customers. Fluent in Mandarin and English (TOEFL: 105/120).

[email protected]
+886-921672917
Hsinchu, Taiwan

Engineering Skills

PHYSICAL DESIGN
  • Establish and deploy physical design methodology in advanced nodes (7/6/5/4/3nm)
  • Design implementation from netlist to tape-out and PPA assessment in 7/6/5/4/3nm technologies
  • Proven knowledge of Cadence Innovus and Synopsys ICC2/FusionCompiler backend design flow
  • Familiar with Ansys Redhawk/Redhawk-CPA EM/IR methodology
CUSTOMER ENGAGEMENT, SUPPORT, and EDUCATION
  • Coordinate technical support to customers in the above areas of profession
  • Proactive and close collaboration with EDA vendors
  • Conduct technological training courses and technical application notes for partners/customers

Education

NATIONAL CHIAO TUNG UNIVERSITY, 2011 - 2013

M. Sc. of Electronics Engineering

NATIONAL CHIAO TUNG UNIVERSITY, 2007 - 2011

B.S. of Electronics Engineering

Professional Experience

INTEL CORPORATION, 2022 - Present

Physical Design Engineer, Design Service Engineering


  • 3DIC testchip execution
  • Heterogeneous integration flow enablement

TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD., 2019 - 2022

Principal Eningeer, Design Technology Platform


  • 6nm HPC segment customer engagement, flow pipeclean, and project on-site field support
  • 5/4/3nm HPC segment customer engagement, PPA assessment, and technical support
  • 5/4/3nm node EDA enablement and certification program
  • 20+ physical implementation flow trainings to customers in 7/6/5/3 nm technologies

GLOBAL UNICHIP CORPORATION, 2013 - 2019

Deputy Technical Manager, Design Service


  • 7nm HPC peripheral block implementation (2M inst.; P&R, timing closure, DRC/LVS)
  • 7nm GPU block implementation (1M inst.; P&R, path-finding, customer field support)
  • 7nm physical design flow and DDR IP hardening (P&R, timing closure, DRC/LVS, field support)
  • 5+ power integrity analysis projects in 28/16nm technology
  • 20+ APR and/or power integrity project support experience in sub-28nm nodes