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Avatar of 林雨虹.
Avatar of 林雨虹.
品管∕品保工程師 @燁聯鋼鐵股份有限公司
2021 ~ Hiện tại
化學工程師/品管工程師/研發工程師
Hơn một năm
產品品質管制監控、分析儀器操作 企業資源規劃管理(ERP) MM物料管理(Material Management) 制定TWI(Training Within Industry) 工廠營運管制系統 MES(Manufacturing Execution System) X-WIN Cadence - Virtuoso Calibre - DRC、LVS 、LPE HSPICE、 Cscope 證照 基本創傷救命術(BLS) 初級救護技術員(EMT1) 細胞生物實驗室品質及安全管理師 產物保險業務員、 人身
原料及產品品質管制監控、分析儀器操作
企業資源規劃管理(ERP)
MM物料管理(Material Management)
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6-10 năm
國立高雄科技大學 National Kaohsiung University of Science and Technology
半導體工程

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Technical Skills
Specialized knowledge and expertise within the profession (e.g. familiar with SEO and use of related tools).
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Hơn một năm
台灣新北市
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台灣台北市, 台灣新北市, 台灣新竹縣
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國立台灣師範大學
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電機工程學系
In
Profile 00 00@2x

何泰廷

在碩班兩年時間,透過每次設計電路和下線來累積我對電路設計的了解。

0923-607-735
新北市,台灣

[email protected]

學歷

國立臺灣師範大學,2019 年 8月 - 至今

    電機工程學系 


指導教授/實驗室: 蔡政翰 博士/ 射頻微波積體電路實驗室 

碩士論文: 應用於第五代行動通訊之接收機設計

國立宜蘭大學,2015 年 8 月 - 2019 年 7 月

    電子工程學系

經歷

電子學實驗二 助教,2021 年 2 月 - 2021 年 6 月

協助教師授課後課堂Demo當週實驗,並提供解決學生課堂問題,課後批改作業。

射頻主動電路設計與量測實務,2021 年 2 月 - 2021 年 6 月

協助教師授課後課堂Demo實驗,並提供解決學生課堂問題,課後批改作業。

參與台灣半導體研究中心晶片設計課程,2021 年 3 月 17 日 

mmWave Active Electronically Scanned Array design with 3D EM 

電磁學 助教,2020 年 9 月 - 2021 年 1 月 

協助教師授課後解決同學課程相關問題,批改作業。

Sub-6GHz/mmW之共構多輸入輸出射頻模組課程推廣工作訪,2020 年 9 月 3 日 

參與教育部5G行動寬頻人才培育計畫(5G天線與射頻技術聯盟中心)

高階調變技術毫米波寬頻高鏡像抑制收發器研發,2020 年 6 月 - 2021 年 9 月

參與實驗室計畫研究降頻器之高鏡像訊號抑制接收器

電子學實驗二 助教,2020 年 2 月 - 2020 年 6 月 

協助教師授課後課堂Demo當週實驗,並提供解決學生課堂問題,課後批改作業。

技能

Cadence Virtuoso, Advanced Design System, Sonnet, EDA

相關修習課程

射頻與微波積體電路,多輸入多輸出通訊傳收機設計與實作,射頻主動電路設計與量測實務

設計和下線經驗

28GHz Two Stage Low Noise Amplifier using 0.18-um CMOS process


28GHz Up Conversion using 90-nm CMOS process


38GHz Two Stage Power Amplifier using 65-nm CMOS process


• 28GHz Down Conversion using 65-nm CMOS process(碩論電路)


28GHz Receiver using 65-nm CMOS process(碩論電路)


28GHz Down Convertion using 0.18-um CMOS process


28GHz Two Stage Low Noise Amplifier using 65-nm CMOS process


38GHz Variable Gain Amplifier with BandGap using 65-nm CMOS process


3GHz Variable Gain Amplifier using 65-nm CMOS process(碩論電路)


28GHz Two Stage Low Noise Amplifier using 0.18-um CMOS process

Paragraph image 06 00@2x
Paragraph image 06 01@2x
Paragraph image 06 02@2x

・28GHz Down Conversion using 0.18-um CMOS process

Paragraph image 06 00@2x
Paragraph image 06 01@2x
Paragraph image 06 02@2x
Paragraph image 06 00@2x

・28GHz Up Converter using 90-nm CMOS process

Paragraph image 06 00@2x
Paragraph image 06 01@2x
Paragraph image 06 02@2x
Paragraph image 06 00@2x
Paragraph image 06 01@2x
Paragraph image 06 02@2x
28GHz Two Stage Low Noise Amplifier using 65-nm CMOS process

Paragraph image 06 00@2x
Paragraph image 06 01@2x
Paragraph image 06 02@2x
38GHz Two Stage Power Amplifier using 65-nm CMOS process

Paragraph image 06 00@2x
Paragraph image 06 01@2x
38GHz Variable Gain Amplifier with BandGap using 65-nm CMOS process

Paragraph image 06 00@2x
Paragraph image 06 01@2x
28GHz Down Conversion using 65-nm CMOS process(碩論電路)

Paragraph image 06 00@2x
Paragraph image 06 01@2x
Paragraph image 06 02@2x
Paragraph image 06 00@2x
3GHz Variable Gain Amplifier using 65-nm CMOS process(碩論電路)

Paragraph image 06 00@2x
Paragraph image 06 01@2x
28GHz Receiver using 65-nm CMOS process(碩論電路)

Paragraph image 06 00@2x
Paragraph image 06 01@2x
Paragraph image 06 02@2x
Paragraph image 06 00@2x

證照


工業電子丙級,AMA先進為控制器應用認證

Resume
Hồ sơ của tôi
Profile 00 00@2x

何泰廷

在碩班兩年時間,透過每次設計電路和下線來累積我對電路設計的了解。

0923-607-735
新北市,台灣

[email protected]

學歷

國立臺灣師範大學,2019 年 8月 - 至今

    電機工程學系 


指導教授/實驗室: 蔡政翰 博士/ 射頻微波積體電路實驗室 

碩士論文: 應用於第五代行動通訊之接收機設計

國立宜蘭大學,2015 年 8 月 - 2019 年 7 月

    電子工程學系

經歷

電子學實驗二 助教,2021 年 2 月 - 2021 年 6 月

協助教師授課後課堂Demo當週實驗,並提供解決學生課堂問題,課後批改作業。

射頻主動電路設計與量測實務,2021 年 2 月 - 2021 年 6 月

協助教師授課後課堂Demo實驗,並提供解決學生課堂問題,課後批改作業。

參與台灣半導體研究中心晶片設計課程,2021 年 3 月 17 日 

mmWave Active Electronically Scanned Array design with 3D EM 

電磁學 助教,2020 年 9 月 - 2021 年 1 月 

協助教師授課後解決同學課程相關問題,批改作業。

Sub-6GHz/mmW之共構多輸入輸出射頻模組課程推廣工作訪,2020 年 9 月 3 日 

參與教育部5G行動寬頻人才培育計畫(5G天線與射頻技術聯盟中心)

高階調變技術毫米波寬頻高鏡像抑制收發器研發,2020 年 6 月 - 2021 年 9 月

參與實驗室計畫研究降頻器之高鏡像訊號抑制接收器

電子學實驗二 助教,2020 年 2 月 - 2020 年 6 月 

協助教師授課後課堂Demo當週實驗,並提供解決學生課堂問題,課後批改作業。

技能

Cadence Virtuoso, Advanced Design System, Sonnet, EDA

相關修習課程

射頻與微波積體電路,多輸入多輸出通訊傳收機設計與實作,射頻主動電路設計與量測實務

設計和下線經驗

28GHz Two Stage Low Noise Amplifier using 0.18-um CMOS process


28GHz Up Conversion using 90-nm CMOS process


38GHz Two Stage Power Amplifier using 65-nm CMOS process


• 28GHz Down Conversion using 65-nm CMOS process(碩論電路)


28GHz Receiver using 65-nm CMOS process(碩論電路)


28GHz Down Convertion using 0.18-um CMOS process


28GHz Two Stage Low Noise Amplifier using 65-nm CMOS process


38GHz Variable Gain Amplifier with BandGap using 65-nm CMOS process


3GHz Variable Gain Amplifier using 65-nm CMOS process(碩論電路)


28GHz Two Stage Low Noise Amplifier using 0.18-um CMOS process

Paragraph image 06 00@2x
Paragraph image 06 01@2x
Paragraph image 06 02@2x

・28GHz Down Conversion using 0.18-um CMOS process

Paragraph image 06 00@2x
Paragraph image 06 01@2x
Paragraph image 06 02@2x
Paragraph image 06 00@2x

・28GHz Up Converter using 90-nm CMOS process

Paragraph image 06 00@2x
Paragraph image 06 01@2x
Paragraph image 06 02@2x
Paragraph image 06 00@2x
Paragraph image 06 01@2x
Paragraph image 06 02@2x
28GHz Two Stage Low Noise Amplifier using 65-nm CMOS process

Paragraph image 06 00@2x
Paragraph image 06 01@2x
Paragraph image 06 02@2x
38GHz Two Stage Power Amplifier using 65-nm CMOS process

Paragraph image 06 00@2x
Paragraph image 06 01@2x
38GHz Variable Gain Amplifier with BandGap using 65-nm CMOS process

Paragraph image 06 00@2x
Paragraph image 06 01@2x
28GHz Down Conversion using 65-nm CMOS process(碩論電路)

Paragraph image 06 00@2x
Paragraph image 06 01@2x
Paragraph image 06 02@2x
Paragraph image 06 00@2x
3GHz Variable Gain Amplifier using 65-nm CMOS process(碩論電路)

Paragraph image 06 00@2x
Paragraph image 06 01@2x
28GHz Receiver using 65-nm CMOS process(碩論電路)

Paragraph image 06 00@2x
Paragraph image 06 01@2x
Paragraph image 06 02@2x
Paragraph image 06 00@2x

證照


工業電子丙級,AMA先進為控制器應用認證