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the TCP module, improving packet processing efficiency by 30%. Redesign the logging mechanism, increasing the searching and logging efficiency by 90%. Software Engineer • Syntec ( Kernel Architecture Section ) Sep~ DecMaintaining a multi-threaded CNC controller system using C++. Maintaining FPGA communication modules with Xilinx ISE using Verilog. Being the section contact window, classifying reported bugs and providing consulting to other departments. Lead and build up the communication error diagnosis SOP, providing sufficient logging and diagnostics from FPGA and CNC controller without impacting system performance, decreases technical support travel by 50%. Optimizing the EtherCAT