工作職責 (Responsibilities): Build & innovate on high-speed analog/mixed-signal circuits such as PCIe/DDR/HDMI... transmitter and receiver in deep sub-micron CMOS technology for integration in SoC prod...
工作職責 (Responsibilities): Build & innovate on high-speed analog/mixed-signal circuits such as PCIe/DDR/HDMI... transmitter and receiver in deep sub-micron CMOS technology for integration in SoC prod...
[Responsibilities] - ARM series CPU integration -System bus architecture design and implementation [Professional Experience] - Experienced in ARM series CPU integration flow (ARM9, CA7, etc.) - Exp...
[Responsibilities] - ARM series CPU integration -System bus architecture design and implementation [Professional Experience] - Experienced in ARM series CPU integration flow (ARM9, CA7, etc.) - Exp...
Responsibilities: ◆ SoC complete DFT flow including related simulation and STA ◆ Build script including MBIST, DFT compiler and ATPG ◆ Support chip designer to improve chip DFT quality
Responsibilities: ◆ SoC complete DFT flow including related simulation and STA ◆ Build script including MBIST, DFT compiler and ATPG ◆ Support chip designer to improve chip DFT quality
Responsibilities: ◆ SoC complete DFT flow including related simulation and STA ◆ Build script including MBIST, DFT compiler and ATPG ◆ Support chip designer to improve chip DFT quality
Responsibilities: ◆ SoC complete DFT flow including related simulation and STA ◆ Build script including MBIST, DFT compiler and ATPG ◆ Support chip designer to improve chip DFT quality
[Responsibilities] - Work with a team to: 1、Plan design architecture. 2、Develop high quality digital design 3、Be familiar with IC design flow 4、High-speed interface controller design 5、Digital PHY ...
[Responsibilities] - Work with a team to: 1、Plan design architecture. 2、Develop high quality digital design 3、Be familiar with IC design flow 4、High-speed interface controller design 5、Digital PHY ...
[Responsibilities] - Work with a team to: 1、Plan design architecture. 2、Develop high quality digital design. 3、Be familiar with IC design flow. 4、In-house core algorithms' module design - Professio...
[Responsibilities] - Work with a team to: 1、Plan design architecture. 2、Develop high quality digital design. 3、Be familiar with IC design flow. 4、In-house core algorithms' module design - Professio...
[Responsibilities] - Work with a team to: 1、Plan design architecture. 2、Develop high quality digital design. 3、Be familiar with IC design flow. 4、In-house core algorithms' module design - Professio...
[Responsibilities] - Work with a team to: 1、Plan design architecture. 2、Develop high quality digital design. 3、Be familiar with IC design flow. 4、In-house core algorithms' module design - Professio...
工作經驗 (Professional Experience) -Experienced in SoC front-end integration flow -Experienced in sign-off tools such as PTPX, DFT tools, etc. -Experienced in SoC platform/peripheral design 工作職責 (Respo...
工作經驗 (Professional Experience) -Experienced in SoC front-end integration flow -Experienced in sign-off tools such as PTPX, DFT tools, etc. -Experienced in SoC platform/peripheral design 工作職責 (Respo...
工作經驗 (Professional Experience) -Experienced in SoC front-end integration flow -Experienced in sign-off tools such as PTPX, DFT tools, etc. -Experienced in SoC platform/peripheral design 工作職責 (Respo...
工作經驗 (Professional Experience) -Experienced in SoC front-end integration flow -Experienced in sign-off tools such as PTPX, DFT tools, etc. -Experienced in SoC platform/peripheral design 工作職責 (Respo...
[Responsibilities] 1、Netlist-to-GDS design flow. including power plan, floorplan, placement, timing optimization, clock tree synthesis and routing 2、STA timing analysis and fixing 3、Physical verifi...
[Responsibilities] 1、Netlist-to-GDS design flow. including power plan, floorplan, placement, timing optimization, clock tree synthesis and routing 2、STA timing analysis and fixing 3、Physical verifi...
[Responsibilities] 1、Netlist-to-GDS design flow. including power plan, floorplan, placement, timing optimization, clock tree synthesis and routing 2、STA timing analysis and fixing 3、Physical verifi...
[Responsibilities] 1、Netlist-to-GDS design flow. including power plan, floorplan, placement, timing optimization, clock tree synthesis and routing 2、STA timing analysis and fixing 3、Physical verifi...