Timing/IR Signoff Analysis Engineer/Technical Manager

職缺描述

Develop the Timing/IR signoff criterion for leading process node and 3DIC.
Maintain the Timing/IR signoff criterion ,provide issue solving and consultant for projects on abnormal/unfixable timing/IR violation
Develop new Timing/IR signoff methodology to be applied during chip synthesis/APR/STA/IR
SPICE correlation for new timing/IR signoff criterion
Regression test for every signoff methodology by STA violation/slack analysis, IR results
Post-silicon data analysis for silicon-proven timing/IR signoff criterion

職務需求

Knowledge of timing sign-off fundamentals : signal integrity analysis, cross-talk, and OCV (AOCV, POCV) effects, etc. Experience using timing sign-off tools : PrimeTime/Tempus/HSPICE .
Experience in design margin modeling, including CCS/AOCV/POCV/LVF is a plus"
Experience with IR signoff tools like Redhawk-SC, Redhawk, Voltus. Experience in Methodology Development .
Understanding of programming fundamentals and concepts. Proficient programming skills in Python, Tcl , Perl .
Ability to collaborate effectively with different teams . Good communication to describe issues accurately to management.
Familiar with timing/IREM sign-off factors : OCV/IR/thermal/Reliability , and spice simulation. Experience in on-die sensor design is a plus
Experience in exploring and defining new process node sign-off criterion : N7/N5/N3/3DIC is a plus
Familiarity with gate level design flows, such as PGB , place-and-route, schematic/layout design, RC extraction, physical verification is a plus

50K ~ 200K TWD/月

關於我們

聯發科技成立於1997年，透過持續投資先進製程與前瞻技術，現已成長為全球領先的IC設計公司，提供涵蓋智慧手持裝置、智慧家庭應用、無線連結技術及物聯網產品等多個領域的系統晶片整合解决方案(SoC)，並居市場領先地位。聯發科技一年約出貨15億顆晶片落實在上億台的終端產品在全球各地上市。聯發科技提供高度整合與創新性的晶片設計方案，不僅協助製造商優化供應鏈及縮短新產品開發時間，還利於其在全球成熟及發展中市場建立競爭優勢。

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Timing/IR Signoff Analysis Engineer/T...

MediaTek 聯發科技

Timing/IR Signoff Analysis Engineer/Technical Manager

MediaTek 聯發科技

職缺描述

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