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1. ASIC Design or IP Integration 2. Familiar with Digital front-end EDA tool.
1.8M ~ 2.5M TWD / year
3 years of experience required
No management responsibility
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques. Preferred qualifications: Master's de
