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1.高速介面(SerDes)類比電路設計 2.Circuit design of CTLE/CDR/DFE/PLL/TX 3.Familiar with SerDes and DDR PHY architecture (ex: PCIe3 / USB3 / HDMI2 / DDR4 / LPDDR4/4x ...etc)

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree Electrical Engineering, Computer Engineering, or equivalent practical experience. Experience with ATE IC testing, yield and bin Pareto analysis. Preferred qualifications: Experience with Automatic Test Equipment (ATE) test platforms (e.g., Advantest 93K , Teradyne UltraFlex system on a chip (SoC) test system). Experience with SERDES, PCIe, DDR, and mixed-signal circuits (e.g., ADC, DAC, PLL, LDO, and their perfor

1. 使用OrCAD進行數位硬體電路(FPGA, DDR, PCIe, DC-DC power, ADC/DAC...)修改與設計 2. 指導PCB布局工程師完成PCB layout 3. 對所設計之電路測試及除錯, 完成功能和性能驗證 4. 撰寫工程文件進行技轉, 以

工作職責 (Responsibilities)： Build & innovate on high-speed analog/mixed-signal circuits such as PCIe/DDR/HDMI... transmitter and receiver in deep sub-micron CMOS technology for integration in SoC products. Work with digital team on specification definition Create behavior model for analog/digital evaluation Compliance test for SerDes IP