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1. ASIC Design or IP Integration 2. Familiar with Digital front-end EDA tool.

面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)

工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計

負責 高速 PLL 以及 Serdes 相關類比電路開發。 設計PCIe/USB/SATA相關APHY serdes電路，例如：USB4、PCIe5、25G serdes

Develop reusable and reliable software solutions according to project requirements. Improve software architecture and quality. Evaluate functional requirements and develop software solutions. Software design break down and effort estimation. Software design document writing. Lead software design discussion and alignment meeting.

Company highlights 優質美商半導體設備商公司，該領域的領頭羊，相關主要供應鏈如TSMC，都是主要客戶。 良好的薪酬福利、年度績效獎金及調薪、員工優惠認股計畫等，不輸半導體設計公司。 很高的機會能外派到美

Lead the top-level integration of analog IPs, encompassing projects related to SSD, UFS, eMMC, SD, and more. Demonstrate a solid understanding of basic analog circuit design concepts, including but not limited to LDO, DCDC, BANDGAP, Voltage Detector, PLL, ADC, etc. Assist in conducting fail sample analysis and perform IC measurements to contribute to the identification and resolution of issues. If you have a background in analog IP integration, possess a strong grasp of analog circuit design

Circuit board design to full fill each customized or prototyping products; board layout review with full responsibility to guarantee circuit with full functional operation after manufacturing. The whole development period that have to align with internal PMs requirement. Travel, co-operation, technical communication with outside customers, ODMs, OEMs and internal PMs, FWs, EMS is necessary. Be realized what functionalities which required from customers and risks assessment before design kick-off

通訊5G用或資料中心用不斷電系統(BBU)設計 1.切換式電源設計與電池管理系統 2.BBU (battery backup unit) design 3.產品階與系統階規劃設計 4.跨功能團隊溝通協調合作

專長是Class D Amp IP設計的類比IC設計人員協助產品研發, 且相關設計/產品經驗有 10 年以上 。 工作內容： 1. 負責HV Class D Amp新產品的評估, 包含前期的面積評估, 製程比較, 2. 以及中期的Class D Amp IP