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Logo of 智微科技股份有限公司.
1. Verify RTL design with System Verilog and UVM verification methodology. 2. PCIe or USB or SATA related VIP test maintenance and development. 3. Develop verification platform or behavioral models. 4.Test planning, testbench documentation and development.
Verilog
60K ~ 80K TWD / month
No management responsibility

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