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Logo of 浦飛爾科技有限公司.
1.Familiar with RTL design & simulation 2.Familiar with FPGA prototype & emulation 3.Familiar with Verilog coding & ASIC design flow 4.Familiar with Analog and digital co-simulation 5.Familiar with Design documentation 6.Experience in MCU 7.Experience in ADC/DAC is a plus 8.Experience in low poer design flow is a plus 孰悉以下工具: 熟悉 Verilog coding, 與 ASIC design flow 熟悉
780K ~ 2.34M TWD / année
No management responsibility
Logo of 致茂電子.
1.數位電路設計 2.HDL coding(VHDL / Verilog) 3.電路圖繪製Orcad 4.測試程式撰寫 5.產品量產技術移轉
Regular earnings reach NT$40,000
No requirement for relevant working experience
No management responsibility

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