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Hsinchu City, Taiwan
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負責 高速 PLL 以及 Serdes 相關類比電路開發。 設計PCIe/USB/SATA相關APHY serdes電路,例如:USB4、PCIe5、25G serdes
ADC/DAC/Serds/PLL/LDO/BG/DP/HDMI/USB
USB4、PCIe5、25G serdes
PLL
2.5M ~ 4.5M TWD / year
3 years of experience required
No management responsibility
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We are now looking for a Research Scientist - Circuits - New College Graduate. Advanced circuit design is critically important in the post-Moore’s Law age. Without the ability to scale process to increase performance and reduce power, we must rely more and more on creative architectural and underlying circuit solutions to provide continuing advancement from generation to generation. NVIDIA Research is seeking world-class circuit researchers to contribute to the exploration of future high-perform
Verilog
PLL
TGC Europe
No requirement for relevant working experience
No management responsibility
Logo of NVIDIA.
We are now looking for a Senior Research Scientist - Circuits. Advanced circuit design is critically important in the post-Moore’s Law age. Without the ability to scale process to increase performance and reduce power, we must rely more and more on creative architectural and underlying circuit solutions to provide continuing advancement from generation to generation. NVIDIA Research is seeking world-class circuit researchers to contribute to the exploration of future high-performance, low-power
Verilog
PLL
TGC Europe
No requirement for relevant working experience
No management responsibility
Logo of NVIDIA.
We are now hiring for a Senior Mixed-signal Design Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can
Verilog
Mixed-Signal
PLL
5 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
Lead the top-level integration of analog IPs, encompassing projects related to SSD, UFS, eMMC, SD, and more. Demonstrate a solid understanding of basic analog circuit design concepts, including but not limited to LDO, DCDC, BANDGAP, Voltage Detector, PLL, ADC, etc. Assist in conducting fail sample analysis and perform IC measurements to contribute to the identification and resolution of issues. If you have a background in analog IP integration, possess a strong grasp of analog circuit design
2M ~ 4M TWD / year
3 years of experience required
No management responsibility

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