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鄭人瑋 (Ren-Wei Jheng)
IC設計工程師
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鄭人瑋 (Ren-Wei Jheng)

IC設計工程師
我是鄭人瑋,畢業於國立中山大學資訊工程所-系統晶片 (system on chip,SOC)組,研究內容為錯誤更正碼 (error correction codes,ECC),論文題目為「基於三維矩陣的置信傳遞極化碼之VLSI實現」。本人生性樂觀、善於溝通、勇於接受挑戰以及具備數理分析能力等特質。 過去,在學/在職的過程中,我除了努力精進自己的專業能力之外,同時透過教授/主管所提供的各種機會,學習到團隊合作與IC設計相關技術的知識。最後,期許我未來能為社會和公司盡一份心力!
芯屹科技
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國立中山大學
Taiwan

Professional Background

  • Current status
    Employed
    Open to opportunities
  • Profession
    Digital IC Design
  • Fields
    Semiconductor
  • Work experience
    2-4 years (2-4 years relevant)
  • Management
  • Skills
    Verilog
    C
    SystemVerilog
    EDA POWER TOOL: PA PTPX Joules
    EDA SYNTHESIS TOOL: GENUS DC
    TCL SHELL
    AMBA protocol: APB AHB AXI
    Linux
    Other EDA TOOLS
  • Languages
    Chinese
    Fluent
  • Highest level of education
    Master

Job search preferences

  • Desired job type
    Full-time
    Interested in working remotely
  • Desired positions
    數位IC設計工程師
  • Desired work locations
    Taipei City, Taiwan
  • Freelance
    Non-freelancer

Work Experience

IC設計工程師

芯屹科技
Full-time
Jun 2023 - Present
Taipei City, Taiwan
1. To verify FIFO (IP-level) in SystemVerilog Assertion (SVA) - Ongoing a. SystemVerilog understanding and trying (EDA playground/workstation) b. env. building in workstation c. Preparing files of introduction for the team 2. Power analysis There are some power gaps in 2 project design: a. Checking scripts of Design Compiler (little scripts gap, but don't care) b. No activity during synthesis (dynamic power don't care) c. Conclusion: There is no big script issue for power gap and these two designs are different 3. Others: nLint in real project a. env. building and debugging b. set Macros and Rule waving (no need to do that) c. Preparing document which shows team member how to run nLint and check report
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數位IC設計工程師

May 2022 - Feb 2023
10 mos
Hsinchu City, Taiwan, 300
1. AMBA (1) APB, AHB, AXI protocol (2) in-house IP study: a. ahb slv decoder: AHB writing behavior b. ahb slv mux: AHB read behavior c. AXI2AHB d. AXI downsizer e. AXI frequency: aslice, slice, F2S, S2F 2. in-house tool (vDesigner, VDNR) reaserch and env. building in real project based on AMBA protocol. (1) in-house tool reaserch and understanding. (2) Auto-gen RTL in specified AMBA architecture. (3) Communicating with co-workers for fixed/debugging specified AMBA atchitecture. 3. PTPX - power analysis in pre-APR netlist/ post-APR netlist (1) Power understanding and PTPX tool behavior reaserch. (2) PTPX introduction for the team. (3) PTPX env. building and reproducing from real case to new case. 4. Power Artist (PA) - power exploration in early RTL phase. (1) Power understanding and PA tool behavior reaserch. (2) PA introduction for the team. (3) PA env. building and reproducing from real case to new case. 5. RTL coding and IC design concept understanding
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資深應用工程師

Oct 2020 - May 2022
1 yr 8 mos
1. To provide key technical support in digital IC design synthesis products. 2. To demonstrate strong ability and to be hands-on in synthesis, AI synthesis and low power methodology. 3. To run benchmarks, characterize problems, and support key customer engagements. 4. To work with team, customer and R&D on new methodologies and flow refinement. 5. To have real case exercise and.
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替代役

Oct 2019 - Sep 2020
1 yr 0 mos
參與過的工作內容: - 台灣總統大選 - 台灣台中燈會 - 武漢肺炎防疫 - 政府紓困方案 - 關懷癱瘓人士 - 里長補選儀式 - 台中消防演習 - 西屯區登革熱防治會議 - 協助解決公所各項事宜

Education

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Master of Science (MS)
資訊工程所/系統晶片組(SOC)
2016 - 2019
Activities and societies
- 科技部半導體射月計畫: 總計畫名稱: 可即時動態重新組態之深度神經網路設計和應用 參與的子計畫名稱: 深度學習加速器之積體電路架構設計及其在養殖池物件辨識之應用 工作內容: 協助計畫成果展示之介面設計、文案編輯與校正以及邏輯設計編排 - AI智慧養殖計畫: 子計畫名稱: 適用於底棲性水產養殖之影像處理技術 工作內容: 協助計畫記者會展示、系統介面及看板設計校正以及攝影助手 - 日月光產學合作: 支援項目: 機器學習 - 貓狗辨識 工作內容: 協助教授指導學弟製作投影片、 報告呈現技巧以及協助校正內容 - 國科會計畫: 計畫名稱: 極碼解碼器之設計實作與應用 工作內容: 硬體架構設計、文獻數據蒐集以及計畫內容撰寫 - 國立中山大學工學院優良教師: 職稱內容: 特派記者 工作內容: 採訪優良教師、資料蒐集以及文案編輯 - 國立中山大學資工系教授專訪: 職稱內容: 特派記者 工作內容: 採訪指導教授、資料蒐集以及文案編輯 - 中山高醫營隊 內容說明: 提供高中生資工領域的相關訊息,包含醫療大數據、錯誤更正碼、GPU設計、光線追蹤、深度學習以及物件辨識等領域的內容,使他們能夠確立自身未來志向 工作內容: 介紹資工系與實驗室、整合各領域的報告以及資料編輯校正 - 實驗室網站內容設計與維護 - 大學部專題製作實驗助教
Bachelor’s Degree
電子工程系
2012 - 2016