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Graduated with a master's degree in Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D process integration engineer in UMC about 7.7 years of experience; and process integration engineer in TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device
reliability improvement.
Email : azurewind.ece95g@nctu.edu.tw
Phone: 0910-828-616

Research topic: A Digital Calibration Scheme for the Successive Approximation Analog-to-Digital Converter

National Yang Ming Chiao Tung University

Chang Gung University，CGU

R&D process integration engineer

Hsieh Azure

 UMC

14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process develop, yield ramp up and reliability improve. EM life time reach 10,000 years in 1000ppm for specify customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process develop, include rule and test key design
3. 22nm eHV (device operate in 8V-27V) interconnect process develop

台灣台南市

Process integration engineer in 40nm - 90nm mature technology
1. Customer handling ( include new tape-out, low yield analysis, WAT, SPC chart monitor...etc)
2. 20nm process transfer from Hsinchu to Tainan

Hsieh Azure’s posts