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m y
engineer
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m y

engineer
Mixed-Signal Verification: 1. Analog circuit behavioral model (Verilog, Verilog-AMS, SystemVerilog) 2. Design verfivation (Serdes IP, RF IP, Low Power Design) 3. Simulation runtime speed up 4. Workflow automation 5. EDA tools 6. Debug
Logo of the organization.
MediaTek
Logo of the organization.
National Yang Ming Chiao Tung University
Taiwan

Professional Background

  • Current status
    Employed
    ・
    Not open to opportunities
  • Profession
    Digital IC Design
  • Fields
    Semiconductor
  • Work experience
    2-4 years (2-4 years relevant)
  • Management
    None
  • Skills
    Verilog
  • Languages
    Chinese
    ・
    Native or Bilingual
    English
    ・
    Intermediate
  • Highest level of education
    Master

Job search preferences

  • Desired job type
    Full-time
    ・
    Interested in working remotely
  • Desired positions
    Hareware Enginner, Digital IC Engineer
  • Desired work locations
    Taiwan
  • Freelance
    Non-freelancer

Work Experience

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Enginner

MediaTek
・
Full-time
Dec 2019 - Present
Hsinchu, Hsinchu City, Taiwan
Mixed-Signal Verification: 1. Analog circuit behavioral model (Verilog, Verilog-AMS, SystemVerilog) 2. Design verfivation (Serdes IP, RF IP, Low Power Design) 3. Simulation runtime speed up 4. Workflow automation 5. EDA tools 6. Debug

Education

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National Yang Ming Chiao Tung University

Master’s Degree
2016 - 2019