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Min-Yung Wang (Martin)
Hardware Engineer
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Min-Yung Wang (Martin)

Hardware Engineer
Experienced electrical engineer of 5+ years specialized in x86 architecture circuit design and server system integration. Familiar high speed interface and PCB layout review. Skilled in coordinating cross-function team to make design process more efficient and smoothly.
Inspur Taiwan
National Central University
Taiwan

Professional Background

  • Current status
  • Profession
    Hardware Engineer
  • Fields
    Hardware
  • Work experience
    4-6 years (4-6 years relevant)
  • Management
    None
  • Skills
    Cadence OrCAD
    Cadence Allegro
    Cadence Concept HDL
    Word、PowerPoint、Excel、Outlook
    Hardware Troubleshooting
    Hardware Development
    Verilog RTL coding base on Intel Altera CPLD
    Python coding for BOM check
  • Languages
    English
    Fluent
  • Highest level of education

Job search preferences

  • Desired job type
    Interested in working remotely
  • Desired positions
    Hardware Engineer
  • Desired work locations
  • Freelance
    Non-freelancer

Work Experience

Hardware Engineer

Dec 2019 - Present
Developed lntel Whitely platform for 2U general server. Including system card design and system level design from EVT to MP. Design Open19 server system with AMD platform. Including motherboard bring up and system schematic design. Design ODM 2U system with Purley platform system on RFQ and concept stage. Including system card schematic design, layout discussion and review, DFM issue solve, and cable define. Support 2U4N system with AMD platform. Including system card design and troubleshooting.

Senior Hardware Engineer

May 2019 - Dec 2019
8 mos
Developed Broadcom platform switch schematics design. Developed Broadcom high speed PHY module Developed CPU module for high speed switch with Intel Denverton platform. CPLD RTL coding base on Altera CPLD. Measured high speed Signal Integrity (CAUI4/CAUI/XFI/QSGMII/SGMII) .

Senior Hardware Engineer

Sep 2015 - May 2019
3 yrs 9 mos
Developed high-density 2U4N system and OCP system with lntel grantley and purley platform schematics design. Build design module of half-width motherboard Build design module of PCI-E re-timer schematics Developed 25/10GbE high speed Ethernet schematics and layout guide Have experience in overarching ODM project

Education

Master of Physics
2013 - 2015
Bachelor of Physics
2009 - 2013