1. Responsible for IC verification and system integration
2. Design unit test patterns and stress test patterns for flash IP function
3. Design the burn-in flow for qualification testing
4. Experience in multi-processor programming and handshaking
5. Familiar with ARM DS-5 and AndeSight IDE
6. Familiar with FPGA prototyping platform (Xilinx UltraScale and Synopsys HAPS)
7. Experience in running simulation on Cadence Palladium system
8. Have knowledge in ONFI 5.0 data training flow on CTT and LTT interface mode
9. Mainly responsible for ASIC bring-up on EVB and M.2 product
10. Maintain flash AC timing configuration tables for project team usage
11. Develop a visualization tool for measuring flash AC timing to meet the specification
12. Develop OSC and PLL clock source standard APIs
13. Develop a Python tool to auto-run regression for testing patterns
14. Experience in developing Toshiba/Micron SB decoding flow
15. Experience in operating Nand Emulator System
16. Familiar with logical analyzer and oscilloscope usage
Remark : Leave without pay from September 2022 to February 2023