Jul 2020 - Present
Project SM2504
> Build Lint Checker with Git hook scripts, which will automatic execute Spyglass Lint when detecting changes in files.
Project SM2268XT2
> Build FPGA(HAPS-100) Daily Automatic Synthesis Environment with crontab.
> Build HAPS-100 MDM(Multi-Design Mode) Environment, co-work with IT department.
Project SM2508
> Build FPGA(HAPS-80) Daily Automatic Synthesis Environment with crontab.
> ASIC RTL integration with Emacs and SystemVerilog.
> Build Jenkins Environment for SpyGlass Lint/CDC/Power checking.
> Add UPF Verification into ProtoCompiler UC2 flow(HAPS80/100).
> Build ASIC(RTL/Netlist)/FPGA Simulation Environment, including Low Power Verification (UPF) with Makefile&Perl and integrate with Avery PCIe/NVMe and other Models(DRAM/NAND/SPI etc).
> Trail Run on CDNS Genus.
Project SM2282
> co-work with Intel on Optane Controller integration and FPGA relative issues.
> Build ProtoCompiler Netlist simulation for debugging.
> Build Snapshot(using tcl script) for Simulation(VCS/Xcelium) to accelerate the CPU time.
> Build FT test case for Optane Controller.
> Analysis Power and Performance for ASIC with Spyglass.
Others
> Convert TEST MODE document(excel) to Verilog Module(top mux).
> Help building UPF file in hierarchy method.
> Research on RDL converting to CSR module.