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劉柏頡
主任工程師
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劉柏頡

主任工程師
6 years Digital Designer, Familiar with Front-End Tools, including Simulator(VCS/Xcelium), FPGA Synthesis(SNPS Synplify & ProtoCompiler, Xilinx Vivado) and some other tools(SpyGlass, LEC). Having Experience on High-Speed Protocols(USB/PCIe/UniPro). Familiar with Linux/LSF commands and Scripting(Makefile, TCL, Perl, Python).
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Silicon Motion
逢甲大學
台灣新竹市

Professional Background

  • Current status
    Employed
    Ready to interview
  • Profession
    Digital IC Design
  • Fields
    Semiconductor
  • Work experience
    6-10 years (6-10 years relevant)
  • Management
    None
  • Skills
    SystemVerilog
    Xilinx FPGA
    Debugging
    Verilog
    Python
    Perl
    Power Management: Low power verification
    UPF
    TCL
    Makefile
  • Languages
    Chinese
    Native or Bilingual
    English
    Intermediate
  • Highest level of education
    Bachelor

Job search preferences

  • Desired job type
    Full-time
    Interested in working remotely
  • Desired positions
    資深數位工程師
  • Desired work locations
  • Freelance

Work Experience

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主任工程師

Jul 2020 - Present
Project SM2504 > Build Lint Checker with Git hook scripts, which will automatic execute Spyglass Lint when detecting changes in files. Project SM2268XT2 > Build FPGA(HAPS-100) Daily Automatic Synthesis Environment with crontab. > Build HAPS-100 MDM(Multi-Design Mode) Environment, co-work with IT department. Project SM2508 > Build FPGA(HAPS-80) Daily Automatic Synthesis Environment with crontab. > ASIC RTL integration with Emacs and SystemVerilog. > Build Jenkins Environment for SpyGlass Lint/CDC/Power checking. > Add UPF Verification into ProtoCompiler UC2 flow(HAPS80/100). > Build ASIC(RTL/Netlist)/FPGA Simulation Environment, including Low Power Verification (UPF) with Makefile&Perl and integrate with Avery PCIe/NVMe and other Models(DRAM/NAND/SPI etc). > Trail Run on CDNS Genus. Project SM2282 > co-work with Intel on Optane Controller integration and FPGA relative issues. > Build ProtoCompiler Netlist simulation for debugging. > Build Snapshot(using tcl script) for Simulation(VCS/Xcelium) to accelerate the CPU time. > Build FT test case for Optane Controller. > Analysis Power and Performance for ASIC with Spyglass. Others > Convert TEST MODE document(excel) to Verilog Module(top mux). > Help building UPF file in hierarchy method. > Research on RDL converting to CSR module.
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資深工程師

Sep 2017 - Jul 2020
2 yrs 11 mos
使用Verilog 進行RTL設計與驗證 使用SystemVerilog 進行驗證 使用python & makefile建立部分Project 環境 負責UHS-I 維護與修正 負責UniPro & MPHY 維護與修正 負責USB3 Gen1&2 維護與修正 提供FPGA 相關驗證與工具 負責部份客戶相關的產品處理 Project JMS901 使用M31 MPHY 於FPGA 平台驗證,並與對方AE合作 分析UniPro/UFS Trace並協助 Performance 提升 分析UHS-I Trace並協助 Performance 提升 協助CP FT驗證 負責ECO A0 所有已知錯誤 Project JMS580 分析客戶端使用上會有誤寫Register 之情況,並提供分析報告與改善方式 Project JMS583 分析A0 與 A2 於VBUS變化時之差異,並提供ECO method 與 FW 防止方式 Project JMS581 評估UHS-I DDR200 可行性,評估SD7.0由UHS-I 轉為PCIE Hardware 可行性 Project JMS586 於FPGA 驗證USB 3.2 PHY Board 之功能性 協助Analog 部門分析特性 因FPGA(V7) 限制,修正PCS部分電路,增加CDC電路改善Timing Violation 提供FPGA I/O 於250MHz 的Data 取樣方式 提供UltraScale+ 驗證環境 提供lane de-skew method 給USB MAC 實作FT Self LoopBack method 整合FPGA 與 ASIC top module

技術行銷工程師

Jun 2015 - Oct 2016
1 yr 5 mos
負責Power IC 驗證與客戶端處理 負責Audio IC 驗證與客戶端處理 蒐集客戶端需求與市場開發

Education

Master’s Degree
電子工程
2011 - 2013
Description
肄業
Bachelor’s Degree
電子工程
2005 - 2010