1). Development of process scaling conditions and abnormal resolution NOR Flash: 110/ 75/ 55 nm NAND Flash: 36 /19 nm 3D NAND Flash: 96L / 192L 2). Survey new materials, tool and software 3). New product mask verification and new process development experiment. (Margin Check) 4). Maintain product yield and solve the problem of low yield by experiment. (Product defect improvement yield increase) 5). The project experiment in the yellow light area and the solution for finding abnormality online. 6).Experienced tool (Knowledge and Recipe setting): Expose: ASML (193Dry/ 193immersion), Canon. Metrology: CDSEM(Hitachi, Apply) Overlay (KLA) 7).Analysis and design for Litho mark . 8).Tool simulation: SMO/PROLITHUS/PRODATA 9).SPIE paper: Reducing the substrate dependent scanner leveling effect in low-k1 contact printing

1). Development of process scaling conditions and abnormal resolution NOR Flash: 130/90/58 nm Logic: 180 nm 2). Development and maintenance of SOPs and technical documents related to the yellow light area process. 3). Yellow light area process control (SPC JOB setup, SPC Control) 4). The safety improvement of semiconductor yellow light process.