Sep 2020 - Present
Debug Team
Responsibility: Develop and support debug functionality for SystemVerilog and VHDL simulator
- FSDB Optimization of Long Fan-in Signal reading | 2021 Mar. - 2021 May
-- Pruning signal reconstruction and detecting feedback loop in the signal network
-- Speedup for reading signals is up to 1000X
- Intermediate Representation (IR) Cleanup and Readback Testing - 2021 Sep. - 2022 Jan.
-- Build up the tests for IR cleanup and readback to improve test coverage
-- Find the root cause and build an in-house case for the crash in the customer's design
- Random Test Generating (Quality Project) | 2020 Oct. - Now
-- Support FSDB dumping test
-- Improve code coverage in debug functionality
- Build documentation for new employee training | 2020. Sep - Now
-- Write down the steps for infrastructure setup and the usage of in-house tools
-- Reduce about 50% efforts for the new employee training
-- Collect and organize common issues and frequently used options in developing and debugging