VCS - verilog compile simulator (C++, C, Compiler Optimization, Python) • Developed and supported debug functionality for SystemVerilog compile simulator • Parallelized design traversal in FSDB dumping, speeding up runtime by 3x with multithreading • Optimized FSDB gate-data loading and reduced 10-60% runtime memory footprint, benefiting customers running hundreds-of-GB designs with tight memory budgets • Initiated a project to migrate STL hash tables to Abseil Swiss tables for a millions-line code base, reducing up to 70% peak memory usage and speeding up hash table queries by 100% • Debugged and resolved urgent customer issues in tight timelines (< 1 day TAT) with limited information, tools, and access to the environment

Voda Scheduler: GPU scheduler for elastic/distributed deep learning workloads in Kubernetes cluster https://github.com/heyfey/vodascheduler (30+ stars) (Golang, Python, Distributed Systems) • Designed and built a GPU scheduler on top of Kubernetes and several open-source projects using microservices architecture • Sped up overall training time by 2.38x and increased cluster utilization by 1.4x with -- State-of-the-art scheduling algorithms with resource elasticity -- Topology-aware scheduling & worker migration to consolidate resources • Designed and implemented the heterogeneous scheduling, auto-scaling, and fault-tolerant mechanisms for the system

(C, Python, Machine Learning) • Designed algorithm & firmware for real-time embedded system • Introduced machine learning and data visualization to automate issue analysis, saving 90% of human effort