Jan 2022 - Present
VCS - verilog compile simulator
(C++, C, Compiler Optimization, Python)
• Developed and supported debug functionality for SystemVerilog compile simulator
• Parallelized design traversal in FSDB dumping, speeding up runtime by 3x with multithreading
• Optimized FSDB gate-data loading and reduced 10-60% runtime memory footprint, benefiting customers running hundreds-of-GB designs with tight memory budgets
• Initiated a project to migrate STL hash tables to Abseil Swiss tables for a millions-line code base, reducing up to 70% peak memory usage and speeding up hash table queries by 100%
• Debugged and resolved urgent customer issues in tight timelines (< 1 day TAT) with limited information, tools, and access to the environment