• Teaching assistant of AI Computing Architecture and System course. • Designed a series of teaching material focused in RISC-V CPU design, RISC-V emulator, memory-mapped AI accelerator using systolic array and AXI bus design. • Overhauled the open-source code and transferred the context became suitable for education. Selected Projects Accelerated Convolutional Neural Network (CNN) on FPGA , Verilog, Python Jul. 2021 • Designed and conducted a hardware-accelerated CNN model through designing a specific DSP dataflow on FPGA. • Achieved configurable hardware-software co-design by packaging CNN hardware module with AXI IP.