Employment History

RD Engineer at UMC  2015 - Present

1. Resolved gap-fill and step height problems in embedded memory via ALD process improvement.
2. Retrofitted the ALD process from the liquid delivery system to the new delivery system for defect reduction.
   • ALDOX usually has defect issues due to its precursor 2NTE being easy to condense in the liquid delivery system. The vendor has already developed a vapor delivery system to solve this problem. I evaluated and optimized recipes in this new system to match our company's criteria.
3. Developed flowable low k material to optimize several processes for embedded memory applications.
   • Gap-fill and step high control between logic and memory area are a big challenge in embedded memory due to bad flowability and step coverage of ULK deposition. The vendor developed a novel material with low dielectric constant and good flowability, i.e., flowable low k material, which may answer this challenge. I directed the vendor to optimize the flowable low k material recipe to fit our embedded memory process. Finally, the step high only had < 50 A by AFM. (BKM was 200A)
4. Improved antenna effect in 22 nm technology by tuning plasma uniformity in ULK deposition.
   • The antenna effect is a reliability problem in the BEoL due to plasma-induced damage from the etch or deposition process. According to big data analysis, ULK deposition plays a major role in 22 nm technology. We did trial and error to optimize pressure/precursor flow/spacing/carrier gas/ temperature/ ramp rate/power...etc. Finally, we reduced the antenna failure rate from 20% to almost zero by optimizing plasma uniformity in ULK deposition.  
     
5. Troubleshooting in dielectric process for 14 nm and 22 nm mass product.
6. Optimized ULK film for 28 nm shrinkage to 22 nm technology.
7. Developed high compressive TEOS for wafer bonding. ( < -350 MPa)
8. Developed Ar carrier gas in TEOS deposition for helium reduction.