process development Process integration engineer • Taiwan Semiconductor Manufacturing Company(TSMC) JulyApril 2014 Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies 1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart) 2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development EducationNational Yang Ming Chiao Tung University Electrical Engineering & IC designChang Gung University,CGU Electrical Engineering Department Personal advantage Strong learning ability Good at teamwork High problem solving ability Skills Reliability improvement Defect reduction Process Integration
National Yang Ming Chiao Tung University・
Electrical Engineering & IC design