Tainan City, Taiwan
Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement.
Email : [email protected]
Phone: 0910-828-616
June 2014 - March 2022
14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process development, yield ramp up and reliability improve. EM life time reaches 10,000 years at the 1000ppm specified customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process development, includes rules and test key design
3. 22nm eHV (device operating in 8V-27V) interconnect process development
July 2010 - April 2014
Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies
1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart)
2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development
2006 - 2009
2002 - 2006
Japanese — Elementary
Tainan City, Taiwan
Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement.
Email : [email protected]
Phone: 0910-828-616
June 2014 - March 2022
14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process development, yield ramp up and reliability improve. EM life time reaches 10,000 years at the 1000ppm specified customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process development, includes rules and test key design
3. 22nm eHV (device operating in 8V-27V) interconnect process development
July 2010 - April 2014
Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies
1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart)
2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development
2006 - 2009
2002 - 2006
Japanese — Elementary