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4 到 6 年
6 到 10 年
10 到 15 年
15 年以上
Avatar of Shu-Wei Liu.
Avatar of Shu-Wei Liu.
Senior Engineer @Taiwan Semiconductor Manufacturing Company(TSMC)
2022 ~ 現在
詳談
一個月內
Shu-Wei Liu Software Engineer at Singular Wings Medical. A creative problem-solver with solid programming skill possesses 7-year experience as a software engineer. Have been develop C# in .Net environment for 6-years and developing python now. Good at flow design, CI/CD, data structure design, system maintenance, problem analysis and T-SQL performance tuning. Experienced in Amazon Web Services, Google Cloud Platform, Jenkins, GitHub Actions, Azure Application Insights and Amazon CloudWatch. Familiar with Scrum, Unit Test, Integration Test and web API development. Hsinchu, Taiwan Skills Programming C#
System Design
ASP.NET MVC
AngularJS
就職中
目前會考慮了解新的機會
全職 / 對遠端工作有興趣
10 到 15 年
Yuan Ze University
Bachelor of Computer Science and Engineering
Avatar of the user.
Avatar of the user.
Senior Engineer @Taiwan Semiconductor Manufacturing Company(TSMC)
2024 ~ 現在
R&D Engineer
一個月內
C Programming
C++ Programming
Git
就職中
目前沒有興趣尋找新的機會
全職 / 對遠端工作有興趣
6 到 10 年
National Central University
Mechanical Engineering
Avatar of Hsieh Azure.
離線
Avatar of Hsieh Azure.
離線
曾任
R&D process integration engineer @ UMC
2014 ~ 2022
Semiconductor Engineer
超過一年
ramp up and reliability improve. EM life time reaches 10,000 years at the 1000ppm specified customer requested 2. BEoL interconnect (pitch 52nm, SADP-DUV) process development, includes rules and test key design 3. 22nm eHV (device operating in 8V-27V) interconnect process development Process integration engineer • Taiwan Semiconductor Manufacturing Company(TSMC) JulyApril 2014 Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies 1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart) 2. Advanced technology node: 20nm process transfer from Hsinchu to
Excel
reliability
Process Integration
待業中
目前沒有興趣尋找新的機會
全職 / 對遠端工作有興趣
10 到 15 年
National Yang Ming Chiao Tung University
Electrical Engineering & IC design
Avatar of the user.
Avatar of the user.
Metrology Engineer (OCD) @Taiwan Semiconductor Manufacturing Company(TSMC)
2018 ~ 現在
Metrology Engineer
超過一年
Optical measurement
cdsem
Metrology
全職 / 對遠端工作有興趣
6 到 10 年
National Chiao Tung University
Display Institute
Avatar of the user.
Avatar of the user.
曾任
Senior process engineer @Taiwan Semiconductor Manufacturing Company (TSMC)
2009 ~ 2021
Etch process engineer
超過一年
Specifications
Cost Benefit
Root Cause
待業中
全職 / 對遠端工作有興趣
10 到 15 年
TUNGHAI UNIVERSITY
應用化學系
Avatar of CC Hsu.
Avatar of CC Hsu.
warehouse technician @Taiwan Semiconductor Manufacturing Company(TSMC)
2015 ~ 2019
倉儲管理師
超過一年
CC Hsu Career objective warehouse specialist with 4 years of experience organizing, presentations, preparing facility reports of warehouse, and maintain the positive and attentive. Possess a various of skill of warehouse and office. Still promoting myself of knowledge and experience into a role as a great warehouse specialist. Contact [email protected]. 7, 6F., No. 36, Nanshun 6th St., Lujhu Dist., Taoyuan City 338, Taiwan (R.O.C.) Work experience Taiwan Semiconductor Manufacturing Company(TSMC), warehouse technician, Aug 2015 ~ Mar 2019 A day-shift team's leader
word
excel
powerpoint
全職 / 對遠端工作有興趣
6 到 10 年
Feng Chia university
foreign language(English)
Avatar of 林庭揚.
Avatar of 林庭揚.
Process Integration Engineer @Taiwan Semiconductor Manufacturing Company
2014 ~ 現在
Product Engineer
一年內
graduate school and in the company. I hope that I have opportunity to try my best for your company with my extensive experience. Process Integration Engineer, TSMC, Tainan, Taiwan [email protected] Semiconductor (5nm~90nm) Device engineering Semiconductor Process WAT Analysis Yield Analysis Process Quality Test Manufacturing Statistical Process Control (SPC) Cp/Cpk Failure Mode and Effects Analysis (FMEA) Design of Experiments (DOE) PDCA 3-Leg-5-Why 8D Pareto Chart Box Plot & Normal Quantile Plot Failure Analysis Tool JMP software Transmission Electron Microscopy (TEM) Energy-dispersive X-ray spectroscopy (EDX) Work Experience TSMC, Process
全職 / 對遠端工作有興趣
4 到 6 年
Cheng Kung University
Electrical Engineering
Avatar of John Chiu.
Avatar of John Chiu.
曾任
AI Project Coordinator @TSMC
2020 ~ 現在
雲端工程師,雲端架構師
超過一年
Semiconductor Manufacturing Company @ Machine-learning-based DoE (D esign o f E xperiments ) Consult 10+ process recipe tuning projects in advanced technology (N3, N2, N1.4) Build up a machine-learning adoption framework to assist used OFAT to MFAT tuning. Data Scientist, 8 years 3 months Taiwan Semiconductor Manufacturing Company @ Ma chine Learning Solution Development Using OpenCV(C#), ImageJ (Java) and MATLAB for defect image identification by SVM and K-means, the solution provides a 100% defect identification rate and improves the cycle time from weekly to daily. Leverage scikit-learn (Python) to
Word
Google Drive
Excel
待業中
全職 / 對遠端工作有興趣
6 到 10 年
National Taiwan University
Industrial Engineering
Avatar of 洪維澤.
Avatar of 洪維澤.
EUV Equipment Engineer @台灣積體電路製造股份有限公司
2017 ~ 現在
Mechanical / Thermal Engineer, Semiconductor Engineer
一年內
., Taichung City 403, Taiwan (R.O.C.) My name is Philip. I have 3 years consumer production mechanical and thermal engineer experience. Was responsible for thermal design judgement and implement solution in early product stage. In addition, having 3 years experience as a semiconductor equipment engineer at TSMC strengthens my ability to adapt intense work environment. As a member of lithography process (EUV) department, solving issues for wafer manufacturing timely and precisely improves my professional and communicative skills. Mechanical & Thermal dsign Engineer / EUV Equipment Engineer Semiconductor Manufacture (TSMC) Equipment - ASML
Auto CAD
COMSOL
CAD/CAM
全職
4 到 6 年
National Chiao Tung University
Master of Mechanical engineering
Avatar of 郭哲銘(Galen Kuo).
Avatar of 郭哲銘(Galen Kuo).
Optimization Algorithm Engineer @Taiwan Semiconductor Manufacturing 台灣積體電路製造股份有限公司
2020 ~ 現在
Algorithm Designer
一年內
郭哲銘(Galen Kuo) Algorithm Designer • [email protected] Operation Research / Machine Learning / Algorithm / Optimization Modeling • Cultivated with statistical learning, artificial Intelligence, linear programming, production and manufacturing management and other quantitative reasoning fields. • Work on and Explore occupations related to algorithms, combinatorics and optimization. • Eager to explore and analyze data to support business finding potential knowledge and insight through optimization technique and data analysis method A resourceful operation analyst with sharp quantitative and programming skills possesses 3-year experience deal with optimization problem in Semiconductor Company, TFT-LCD Panel Industry, specialty memory
C++
Combinatorial Optimization
Operation Research
就職中
全職 / 對遠端工作有興趣
4 到 6 年
National Taiwan University
Industrial Engineering

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該領域中具備哪些專業能力(例如熟悉 SEO 操作,且會使用相關工具)。
問題解決能力
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超過一年
R&D process integration engineer
Logo of  UMC.
UMC
2014 ~ 2022
Tainan, 台灣
專業背景
目前狀態
待業中
求職階段
目前沒有興趣尋找新的機會
專業
電子工程師, 製程工程師, I&C 工程師
產業
電子 / 電信, 奈米科技, 半導體
工作年資
10 到 15 年
管理經歷
技能
Excel
reliability
Process Integration
Yield Enhancement
Failure Analysis
語言能力
English
中階
Japanese
初階
求職偏好
希望獲得的職位
Semiconductor Engineer
預期工作模式
全職
期望的工作地點
Tainan, Taiwan, Kaohsiung City, 台灣
遠端工作意願
對遠端工作有興趣
接案服務
學歷
學校
National Yang Ming Chiao Tung University
主修科系
Electrical Engineering & IC design
列印

謝宗殷 (Azure)

R&D technical manager

  Tainan City, Taiwan

Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement.
Email : [email protected]
Phone: 0910-828-616

 

Work experience

R&D technical manager  •   UMC

June 2014 - March 2022

14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process development, yield ramp up and reliability improve. EM life time reaches 10,000 years at the 1000ppm specified customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process development, includes rules and test key design
3. 22nm eHV (device operating in 8V-27V) interconnect process development

Process integration engineer  •  Taiwan Semiconductor Manufacturing Company(TSMC)

July 2010 - April 2014

Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies
1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart)
2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development

Education

2006 - 2009

National Yang Ming Chiao Tung University

Electrical Engineering & IC design

2002 - 2006

Chang Gung University,CGU

Electrical Engineering Department

Personal advantage


  • Strong learning ability
  • Good at teamwork
  • High problem solving ability

Skills


  • Reliability improvement
  • Defect reduction
  • Process Integration
  • Yield Enhancement
  • Failure Analysis

Language


  • English — Intermediate

    Japanese — Elementary

履歷
個人檔案

謝宗殷 (Azure)

R&D technical manager

  Tainan City, Taiwan

Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement.
Email : [email protected]
Phone: 0910-828-616

 

Work experience

R&D technical manager  •   UMC

June 2014 - March 2022

14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process development, yield ramp up and reliability improve. EM life time reaches 10,000 years at the 1000ppm specified customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process development, includes rules and test key design
3. 22nm eHV (device operating in 8V-27V) interconnect process development

Process integration engineer  •  Taiwan Semiconductor Manufacturing Company(TSMC)

July 2010 - April 2014

Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies
1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart)
2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development

Education

2006 - 2009

National Yang Ming Chiao Tung University

Electrical Engineering & IC design

2002 - 2006

Chang Gung University,CGU

Electrical Engineering Department

Personal advantage


  • Strong learning ability
  • Good at teamwork
  • High problem solving ability

Skills


  • Reliability improvement
  • Defect reduction
  • Process Integration
  • Yield Enhancement
  • Failure Analysis

Language


  • English — Intermediate

    Japanese — Elementary