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R&D process integration engineer @ UMC
2014 ~ 2022
Semiconductor Engineer
More than one year
Excel
reliability
Process Integration
Unemployed
Not open to opportunities
Full-time / Interested in working remotely
10-15 years
National Yang Ming Chiao Tung University
Electrical Engineering & IC design
Avatar of Ming-Yao (Mike), Chen.
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External Manufacturing Manager @ONsemiconductor
2018 ~ Present
Managing Director
More than one year
In process control (stability), process capability best practice cross fertilization management. • Promoting yield improvement and systematically feedback information to new product development team, PDCA cycle review. • Actively identify scrap saving opportunities. • Process optimization related to yield loss caused by strict customer requirements and quality case. • Be yield enhancement hub for technical assessment from IC circuit design, wafer manufacturing, assembly, test and OSAT capability evaluation. • Initiate taskforces to drive OSAT on multi-dimensional tasks including customer voice, quality focus, production sustaining. • Lead continuous improvement program to achieve excellent yield and quality performance. • Drive yield
word
powerpoint
Excel
Employed
Full-time / Interested in working remotely
6-10 years
National Chiao Tung University, Hsinchu, Taiwan, Republic of China
Material Science and Engineering
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Past
研發工程師 @新日興股份有限公司
2021 ~ 2023
機械工程師,半導體製程工程師,半導體設備工程師,
Within one month
Word
PowerPoint
Excel
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6-10 years
國立台北科技大學
Materials Science and Engineering
Avatar of 吳明赫.
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Test Equipment Technician @Micron Technology 台灣美光
2018 ~ Present
製程工程師、設備工程師、半導體工程師
Within one month
吳明赫 Test Equipment Technician Taichung City, Taiwan Passionate about continuous learning and professional growth, good at working effectively under pressure, with 10 years of experience in semiconductor back-end equipment. Demonstrates excellence in equipment maintenance, upkeep, improvements and capability enhancements. 工作經歷 Test Equipment Technician Micron Technology 台灣美光 • 十一月Present # Leadership Daily *improvement Equipment UPH/PPJ/MTBF/SDT/UDT KPI, until meet target *Mentor other equipment engineers in the respective area *Support edit/improve Equipment...OCAP/Procedure/SOP
Microsoft Office
critical thinking
Analytical Skills
Employed
Ready to interview
Full-time / Not interested in working remotely
10-15 years
南台科技大學
電機工程系
Avatar of shih-heng sun.
Avatar of shih-heng sun.
Past
Process Integration Engineer @TSMC Fab12B
2019 ~ 2021
Yield Improvement Engineer
More than one year
Shih Heng Sun Semiconductor Process Integration Engineer with 5+ years of experience. TSMC PIE specializing in advanced technology semiconductor products (3nm~10nm). Well-versed in yield improvement of semiconductor manufacturing process, Logic IC yield analysis, and collaborating with production line to solve problems. Making a huge leap for TSMC advanced IC fabrication in process integration and yield improvement. Enthusiastic about semiconductor product development and design which can change people's lives. Work Experiences Yield Improvement Engineer • TSMC Fab12B AugustDecember 2020 Expert in most advanced Logic IC process (5nm~10nm) and familiar with advanced measuring
Communicating
Measuring Instruments
Semiconductor Process
Unemployed
Full-time / Interested in working remotely
4-6 years
National Taiwan University
M.S. Photonics and Optoelectronics
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Project Enginner @ASE Technology Holding Co., Ltd.
2019 ~ Present
QA Engineer
More than one year
Word
Excel
PowerPoint
Employed
Full-time / Interested in working remotely
6-10 years
國立嘉義大學
應用數學, 統計

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More than one year
R&D process integration engineer
Logo of  UMC.
UMC
2014 ~ 2022
Tainan, 台灣
Professional Background
Current status
Unemployed
Job Search Progress
Not open to opportunities
Professions
Electronics Engineer, Process Engineer, I&C Engineer
Fields of Employment
Electronics / Telecommunications, Nanotechnology, Semiconductor
Work experience
10-15 years
Management
None
Skills
Excel
reliability
Process Integration
Yield Enhancement
Failure Analysis
Languages
English
Intermediate
Japanese
Beginner
Job search preferences
Positions
Semiconductor Engineer
Job types
Full-time
Locations
Tainan, Taiwan, Kaohsiung City, 台灣
Remote
Interested in working remotely
Freelance
No
Educations
School
National Yang Ming Chiao Tung University
Major
Electrical Engineering & IC design
Print

謝宗殷 (Azure)

R&D technical manager

  Tainan City, Taiwan

Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement.
Email : [email protected]
Phone: 0910-828-616

 

Work experience

R&D technical manager  •   UMC

June 2014 - March 2022

14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process development, yield ramp up and reliability improve. EM life time reaches 10,000 years at the 1000ppm specified customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process development, includes rules and test key design
3. 22nm eHV (device operating in 8V-27V) interconnect process development

Process integration engineer  •  Taiwan Semiconductor Manufacturing Company(TSMC)

July 2010 - April 2014

Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies
1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart)
2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development

Education

2006 - 2009

National Yang Ming Chiao Tung University

Electrical Engineering & IC design

2002 - 2006

Chang Gung University,CGU

Electrical Engineering Department

Personal advantage


  • Strong learning ability
  • Good at teamwork
  • High problem solving ability

Skills


  • Reliability improvement
  • Defect reduction
  • Process Integration
  • Yield Enhancement
  • Failure Analysis

Language


  • English — Intermediate

    Japanese — Elementary

Resume
Profile

謝宗殷 (Azure)

R&D technical manager

  Tainan City, Taiwan

Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University.
As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience.
Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement.
Email : [email protected]
Phone: 0910-828-616

 

Work experience

R&D technical manager  •   UMC

June 2014 - March 2022

14nm FiNFET BEoL process development, product yield improvement and device reliability improvement
1. BEoL interconnect (pitch 64nm, 2P2E-DUV) process development, yield ramp up and reliability improve. EM life time reaches 10,000 years at the 1000ppm specified customer requested
2. BEoL interconnect (pitch 52nm, SADP-DUV) process development, includes rules and test key design
3. 22nm eHV (device operating in 8V-27V) interconnect process development

Process integration engineer  •  Taiwan Semiconductor Manufacturing Company(TSMC)

July 2010 - April 2014

Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies
1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart)
2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development

Education

2006 - 2009

National Yang Ming Chiao Tung University

Electrical Engineering & IC design

2002 - 2006

Chang Gung University,CGU

Electrical Engineering Department

Personal advantage


  • Strong learning ability
  • Good at teamwork
  • High problem solving ability

Skills


  • Reliability improvement
  • Defect reduction
  • Process Integration
  • Yield Enhancement
  • Failure Analysis

Language


  • English — Intermediate

    Japanese — Elementary