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4-6 years
6-10 years
10-15 years
More than 15 years
Senior Engineer @Taiwan Semiconductor Manufacturing Company(TSMC)2022 ~ Present
・
詳談
Within one month
Shu-Wei Liu Software Engineer at Singular Wings Medical. A creative problem-solver with solid programming skill possesses 7-year experience as a software engineer. Have been develop C# in .Net environment for 6-years and developing python now. Good at flow design, CI/CD, data structure design, system maintenance, problem analysis and T-SQL performance tuning. Experienced in Amazon Web Services, Google Cloud Platform, Jenkins, GitHub Actions, Azure Application Insights and Amazon CloudWatch. Familiar with Scrum, Unit Test, Integration Test and web API development. Hsinchu, Taiwan Skills Programming C#
Employed
・
Open to opportunities
Full-time / Interested in working remotely
10-15 years
Yuan Ze University
・
Bachelor of Computer Science and Engineering
Senior Engineer @Taiwan Semiconductor Manufacturing Company(TSMC)2024 ~ Present
・
R&D Engineer
Within one month
Employed
・
Not open to opportunities
Full-time / Interested in working remotely
6-10 years
National Central University
・
Mechanical Engineering
DevOps Engineer @Foxit Software Inc.2020 ~ 2021
・
DevOps Engineer
Within six months
楊凱淳 Site Reliability Engineer Toufen, Toufen City, Miaoli County, Taiwan 工作經歷 Site Reliability Engineer • Taiwan Semiconductor Manufacturing Company Limited 2021年8月 ~ Site Reliability Engineer • Foxi t Software Inc. MLOps Architecture using Kubeflow Deploying Applications with Docker and Kubernetes 2020年10月年8月 DevOps Engineer • GE MING Digital Media Inc. Building a CI/CD system using GitLab CI and Jenkins Deploying applications using Docker and Kubernetes Setting up a high-availability load balancer using HAProxy and Keepalived Creating a monitoring and log management platform using Prometheus and Graylog
Not open to opportunities
Full-time / Interested in working remotely
10-15 years
Da-Yeh University
・
Computer Science and Information EngineeringPast
R&D process integration engineer @ UMC2014 ~ 2022
・
Semiconductor Engineer
More than one year
Unemployed
・
Not open to opportunities
Full-time / Interested in working remotely
10-15 years
National Yang Ming Chiao Tung University
・
Electrical Engineering & IC design
Metrology Engineer (OCD) @Taiwan Semiconductor Manufacturing Company(TSMC)2018 ~ Present
・
Metrology Engineer
More than one year
Yu-Ta,Wu 6+ years experienced metrology engineer of process technologies at Taiwan Semiconductor Manufacturing Company (N06/N07/N22/Nyears in 6nm/7nm process, found path for optical metrology & quality control. 3+ years in 22nm/28nm litho-related metrology & 2nd mask quality sponsor. Personality, well communicating with cross-department/learning fast/work smart/willing to accept new challenges. Extremely interested in companies located in Taichung/Taipei/Taoyuan or the USA. Taichung City, Taiwan 工作經歷 Metrology Engineer (OCD) • Taiwan Semiconductor Manufacturing Company
Full-time / Interested in working remotely
6-10 years
National Chiao Tung University
・
Display Institute
Past
AI Project Coordinator @TSMC2020 ~ Present
・
雲端工程師，雲端架構師
More than one year
Semiconductor Manufacturing Company @ Machine-learning-based DoE (D esign o f E xperiments ) Consult 10+ process recipe tuning projects in advanced technology (N3, N2, N1.4) Build up a machine-learning adoption framework to assist used OFAT to MFAT tuning. Data Scientist, 8 years 3 months Taiwan Semiconductor Manufacturing Company @ Ma chine Learning Solution Development Using OpenCV(C#), ImageJ (Java) and MATLAB for defect image identification by SVM and K-means, the solution provides a 100% defect identification rate and improves the cycle time from weekly to daily. Leverage scikit-learn (Python) to
Unemployed
Full-time / Interested in working remotely
6-10 years
National Taiwan University
・
Industrial EngineeringPast
Senior process engineer @Taiwan Semiconductor Manufacturing Company (TSMC)2009 ~ 2021
・
Etch process engineer
More than one year
Unemployed
Full-time / Interested in working remotely
10-15 years
TUNGHAI UNIVERSITY
・
應用化學系
Offline
Offline
Process Integration Engineer @Taiwan Semiconductor Manufacturing Company2014 ~ Present
・
Product Engineer
Within one year
experience, and successful Tape-Out new products to 5nm from 90nm and mass production (including logic and more than moore products). Successfully improve product yield through data analysis and DOE, and enhance process tolerance. "Teamwork" is very important to me both in the graduate school and in the company. I hope that I have opportunity to try my best for your company with my extensive experience. Process Integration Engineer, TSMC, Tainan, Taiwan [email protected] Semiconductor (5nm~90nm) Device engineering Semiconductor Process WAT Analysis Yield Analysis Process Quality Test Manufacturing Statistical Process Control (SPC
Full-time / Interested in working remotely
4-6 years
Cheng Kung University
・
Electrical Engineering
EUV Equipment Engineer @台灣積體電路製造股份有限公司2017 ~ Present
・
Mechanical / Thermal Engineer, Semiconductor Engineer
Within one year
N7+ production on EUV - Reduce 25% mask defect - The most safety department of factory Mechanical and Thermal design (Ability Enterprise) Production - Security camera - Consumer camera - Sport/wearing camera Skill - Mechanical design - Thermal design and simulation - CAD/CAM software PTC-creo/COMSOL/Solidworks Customer - Huawei - Google - Sony - Fujifilm Education National Chiao Tung University, Master of mechanical engineering, 2012~2014 National Chung Cheng University, Bachelor of Mechanical engineering, 2008~2012 Work Experience TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY: Aug 2017 ~ Now EUV senior Equipment Engineer ABILITY ENTERPRISE CO., LTD: Aug 2014 ~ Jul 2017 Mechanical and Thermal design Engineer
Full-time
4-6 years
National Chiao Tung University
・
Master of Mechanical engineering
warehouse technician @Taiwan Semiconductor Manufacturing Company(TSMC)2015 ~ 2019
・
倉儲管理師
More than one year
CC Hsu Career objective warehouse specialist with 4 years of experience organizing, presentations, preparing facility reports of warehouse, and maintain the positive and attentive. Possess a various of skill of warehouse and office. Still promoting myself of knowledge and experience into a role as a great warehouse specialist. Contact [email protected]. 7, 6F., No. 36, Nanshun 6th St., Lujhu Dist., Taoyuan City 338, Taiwan (R.O.C.) Work experience Taiwan Semiconductor Manufacturing Company(TSMC), warehouse technician, Aug 2015 ~ Mar 2019 A day-shift team's leader
Full-time / Interested in working remotely
6-10 years
Feng Chia university
・
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Definition of Reputation Credits
Technical Skills
Specialized knowledge and expertise within the profession (e.g. familiar with SEO and use of related tools).
Problem-Solving
Ability to identify, analyze, and prepare solutions to problems.
Adaptability
Ability to navigate unexpected situations; and keep up with shifting priorities, projects, clients, and technology.
Communication
Ability to convey information effectively and is willing to give and receive feedback.
Time Management
Ability to prioritize tasks based on importance; and have them completed within the assigned timeline.
Teamwork
Ability to work cooperatively, communicate effectively, and anticipate each other's demands, resulting in coordinated collective action.
Leadership
Ability to coach, guide, and inspire a team to achieve a shared goal or outcome effectively.
More than one year
Process Integration Engineer @ Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
・
2014 ~ Present
Professional Background
Current status
Job Search Progress
Professions
Other
Fields of Employment
Manufacturing
Work experience
4-6 years
Management
Skills
Languages
Chinese
・
Native or Bilingual
English
・
Fluent
Japanese
・
Beginner
Job search preferences
Positions
Product Engineer
Job types
Full-time
Locations
Hsinchu County, 台灣
Remote
Interested in working remotely
Freelance
Educations
School
Cheng Kung University
Major
Electrical Engineering
林庭揚 (Ting Yang, Lin)
Over 7 years of semiconductor integration experience, and successful Tape-Out new products to 5nm from 90nm and mass production (including logic and more than moore products). Successfully improve product yield through data analysis and DOE, and enhance process tolerance. "Teamwork" is very important to me both in the graduate school and in the company. I hope that I have opportunity to try my best for your company with my extensive experience.
Process Integration Engineer, TSMC,
Tainan, Taiwan
[email protected]
+886 963958505
Skills
Semiconductor (5nm~90nm)
- Device engineering
- Semiconductor Process
- WAT Analysis
- Yield Analysis
- Process Quality Test
Manufacturing
- Statistical Process Control (SPC)
- Cp/Cpk
- Failure Mode and Effects Analysis (FMEA)
- Design of Experiments (DOE)
- PDCA
- 3-Leg-5-Why
- 8D
- Pareto Chart
- Box Plot & Normal Quantile Plot
Failure Analysis Tool
- JMP software
- Transmission Electron Microscopy (TEM)
- Energy-dispersive X-ray spectroscopy (EDX)
Work Experience
TSMC, Process Integration Engineer Nov 2014 ~ Present
- 5nm process experience for new product tape-out, yield/device improvement, process optimization and risk assessment.
- More than moore products' experience including 40/55/80nm high voltage (panel driver),
90nm eDRAM and 65nm automotive products.
- Yield/ device troubleshooting in semiconductor process and coordinating cross team (Module/ Device/ Defect/ Product) to propose possible solution.
- Design, execute and analyze experiment to find out process sweet spot for process window assurance.
- Good for customer management: technical support, successful new tape-out pilot run, device window optimization and continue improvement plan.
- Mass data analysis: inline/WAT/CP/FT data integrated analysis by EDA tool -- Implement FA skill for chip failure mechanism analysis, such as FIB/SEM/TEM/EDX,etc.
Award & Honor (TSMC)
- 2019 1H Engineering Contribution Award (Quality Improvement), 2nd Award, 2019
- Success tape-out customer 1st 40nm HV product, yield is over 90%, and pass customer product quality test.
- (5nm) Found wafer edge low yield caused by rework effect
- (5nm) Found chronic wafer center low yield caused by device profile and tool issue
- (40nm) Found and reduce the device leakage.
- (55nm) Improve wafer edge yield loss due to leakage and process weakness by wafer uniformity increment.
Education
National Cheng Kung University (NCKU)
Master's Degree, Electrical and Electronics Engineering, 2012 ~ 2014
Design and Verification of the Control Procedure of Attitude Determination and Control Subsystem for Nanosatellite.
- Participate 1st cubesat (PACE) make and launch
- Japan Satellite Design Contest: lead graduate and college students to do engineering design
- Phoenix (QB50 project): Be responsible for attitude determination and control system
- Matlab teaching assistant
National Cheng Kung University (NCKU)
Bachelor's's Degree, Systems and Naval Mechatronic Engineering, 2008 ~ 2012
Award & Honor (NCKU)
- The 20th Japan Satellite Design Contest, 1st Award, 2012
- Participate to manufacture 1st nanosatellite by students.
林庭揚 (Ting Yang, Lin)
Over 7 years of semiconductor integration experience, and successful Tape-Out new products to 5nm from 90nm and mass production (including logic and more than moore products). Successfully improve product yield through data analysis and DOE, and enhance process tolerance. "Teamwork" is very important to me both in the graduate school and in the company. I hope that I have opportunity to try my best for your company with my extensive experience.
Process Integration Engineer, TSMC,
Tainan, Taiwan
[email protected]
+886 963958505
Skills
Semiconductor (5nm~90nm)
- Device engineering
- Semiconductor Process
- WAT Analysis
- Yield Analysis
- Process Quality Test
Manufacturing
- Statistical Process Control (SPC)
- Cp/Cpk
- Failure Mode and Effects Analysis (FMEA)
- Design of Experiments (DOE)
- PDCA
- 3-Leg-5-Why
- 8D
- Pareto Chart
- Box Plot & Normal Quantile Plot
Failure Analysis Tool
- JMP software
- Transmission Electron Microscopy (TEM)
- Energy-dispersive X-ray spectroscopy (EDX)
Work Experience
TSMC, Process Integration Engineer Nov 2014 ~ Present
- 5nm process experience for new product tape-out, yield/device improvement, process optimization and risk assessment.
- More than moore products' experience including 40/55/80nm high voltage (panel driver),
90nm eDRAM and 65nm automotive products.
- Yield/ device troubleshooting in semiconductor process and coordinating cross team (Module/ Device/ Defect/ Product) to propose possible solution.
- Design, execute and analyze experiment to find out process sweet spot for process window assurance.
- Good for customer management: technical support, successful new tape-out pilot run, device window optimization and continue improvement plan.
- Mass data analysis: inline/WAT/CP/FT data integrated analysis by EDA tool -- Implement FA skill for chip failure mechanism analysis, such as FIB/SEM/TEM/EDX,etc.
Award & Honor (TSMC)
- 2019 1H Engineering Contribution Award (Quality Improvement), 2nd Award, 2019
- Success tape-out customer 1st 40nm HV product, yield is over 90%, and pass customer product quality test.
- (5nm) Found wafer edge low yield caused by rework effect
- (5nm) Found chronic wafer center low yield caused by device profile and tool issue
- (40nm) Found and reduce the device leakage.
- (55nm) Improve wafer edge yield loss due to leakage and process weakness by wafer uniformity increment.
Education
National Cheng Kung University (NCKU)
Master's Degree, Electrical and Electronics Engineering, 2012 ~ 2014
Design and Verification of the Control Procedure of Attitude Determination and Control Subsystem for Nanosatellite.
- Participate 1st cubesat (PACE) make and launch
- Japan Satellite Design Contest: lead graduate and college students to do engineering design
- Phoenix (QB50 project): Be responsible for attitude determination and control system
- Matlab teaching assistant
National Cheng Kung University (NCKU)
Bachelor's's Degree, Systems and Naval Mechatronic Engineering, 2008 ~ 2012
Award & Honor (NCKU)
- The 20th Japan Satellite Design Contest, 1st Award, 2012
- Participate to manufacture 1st nanosatellite by students.