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進階搜尋
On
沒有符合的項目。
4 到 6 年
6 到 10 年
10 到 15 年
15 年以上
離線
離線
Principal Engineer @TSMC2021 ~ 現在
・
半年內
Kuan-Ting Chen Physical design engineer with 10 years of experience working in the semiconductors industry. Skilled in cell-based ASIC/SoC implementation and power integrity (EM/IR) analysis methodology, especially for advanced nodes (7/6/5/4/3nm). Familiar with Tcl/Perl scripting and design automation. Coordinate technical support and customer engagement with close collaboration with EDA vendors. Organize technological education to partners/customers. Fluent in Mandarin and English (TOEFL: 105/120). [email protected], Taiwan Engineering Skills PHYSICAL DESIGN
就職中
・
目前沒有興趣尋找新的機會
全職 / 對遠端工作有興趣
6 到 10 年
National Chiao Tung University
・
Electronics Engineering最輕量、快速的招募方案，數百家企業的選擇
搜尋履歷，主動聯繫求職者，提升招募效率。
- 瀏覽所有搜尋結果
- 每日可無限次數開啟陌生對話
- 搜尋僅開放付費企業檢視的履歷
- 檢視使用者信箱 & 電話
搜尋技巧
1
嘗試搜尋最精準的關鍵字組合
資深 後端 php laravel
2
將須完全符合的字詞放在雙引號中
"社群行銷"
3
在不想搜尋到的字詞前面加上減號，如果想濾掉中文字，需搭配雙引號使用 (-"人資")
UI designer -UX
職場能力評價定義
專業技能
該領域中具備哪些專業能力（例如熟悉 SEO 操作，且會使用相關工具）。
問題解決能力
能洞察、分析問題，並擬定方案有效解決問題。
變通能力
遇到突發事件能冷靜應對，並隨時調整專案、客戶、技術的相對優先序。
溝通能力
有效傳達個人想法，且願意傾聽他人意見並給予反饋。
時間管理能力
了解工作項目的優先順序，有效運用時間，準時完成工作內容。
團隊合作能力
具有向心力與團隊責任感，願意傾聽他人意見並主動溝通協調。
領導力
專注於團隊發展，有效引領團隊採取行動，達成共同目標。
專業背景
目前狀態
就職中
求職階段
目前沒有興趣尋找新的機會
專業
其他
產業
半導體
工作年資
6 到 10 年
管理經歷
無
技能
語言能力
Chinese
・
母語或雙語
English
・
進階
求職偏好
希望獲得的職位
預期工作模式
全職
期望的工作地點
Taiwan, 台灣
遠端工作意願
對遠端工作有興趣
接案服務
否
學歷
學校
National Chiao Tung University
主修科系
Electronics Engineering
Kuan-Ting Chen
Physical design engineer with 10 years of experience working in the semiconductors industry. Skilled in cell-based ASIC/SoC implementation and power integrity (EM/IR) analysis methodology, especially for advanced nodes (7/6/5/4/3nm). Familiar with Tcl/Perl scripting and design automation. Coordinate technical support and customer engagement with close collaboration with EDA vendors. Organize technological education to partners/customers. Fluent in Mandarin and English (TOEFL: 105/120).[email protected]
+886-921672917
Hsinchu, Taiwan
Engineering Skills
PHYSICAL DESIGN
- Establish and deploy physical design methodology in advanced nodes (7/6/5/4/3nm)
- Design implementation from netlist to tape-out and PPA assessment in 7/6/5/4/3nm technologies
- Proven knowledge of Cadence Innovus and Synopsys ICC2/FusionCompiler backend design flow
- Familiar with Ansys Redhawk/Redhawk-CPA EM/IR methodology
- Coordinate technical support to customers in the above areas of profession
- Proactive and close collaboration with EDA vendors
- Conduct technological training courses and technical application notes for partners/customers
Education
NATIONAL CHIAO TUNG UNIVERSITY, 2011 - 2013
M. Sc. of Electronics Engineering
NATIONAL CHIAO TUNG UNIVERSITY, 2007 - 2011
B.S. of Electronics Engineering
Professional Experience
INTEL CORPORATION, 2022 - Present
Physical Design Engineer, Design Service Engineering
- 3DIC testchip execution
- Heterogeneous integration flow enablement
TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD., 2019 - 2022
Principal Eningeer, Design Technology Platform
- 6nm HPC segment customer engagement, flow pipeclean, and project on-site field support
- 5/4/3nm HPC segment customer engagement, PPA assessment, and technical support
- 5/4/3nm node EDA enablement and certification program
- 20+ physical implementation flow trainings to customers in 7/6/5/3 nm technologies
GLOBAL UNICHIP CORPORATION, 2013 - 2019
Deputy Technical Manager, Design Service
- 7nm HPC peripheral block implementation (2M inst.; P&R, timing closure, DRC/LVS)
- 7nm GPU block implementation (1M inst.; P&R, path-finding, customer field support)
- 7nm physical design flow and DDR IP hardening (P&R, timing closure, DRC/LVS, field support)
- 5+ power integrity analysis projects in 28/16nm technology
- 20+ APR and/or power integrity project support experience in sub-28nm nodes
Kuan-Ting Chen
Physical design engineer with 10 years of experience working in the semiconductors industry. Skilled in cell-based ASIC/SoC implementation and power integrity (EM/IR) analysis methodology, especially for advanced nodes (7/6/5/4/3nm). Familiar with Tcl/Perl scripting and design automation. Coordinate technical support and customer engagement with close collaboration with EDA vendors. Organize technological education to partners/customers. Fluent in Mandarin and English (TOEFL: 105/120).[email protected]
+886-921672917
Hsinchu, Taiwan
Engineering Skills
PHYSICAL DESIGN
- Establish and deploy physical design methodology in advanced nodes (7/6/5/4/3nm)
- Design implementation from netlist to tape-out and PPA assessment in 7/6/5/4/3nm technologies
- Proven knowledge of Cadence Innovus and Synopsys ICC2/FusionCompiler backend design flow
- Familiar with Ansys Redhawk/Redhawk-CPA EM/IR methodology
- Coordinate technical support to customers in the above areas of profession
- Proactive and close collaboration with EDA vendors
- Conduct technological training courses and technical application notes for partners/customers
Education
NATIONAL CHIAO TUNG UNIVERSITY, 2011 - 2013
M. Sc. of Electronics Engineering
NATIONAL CHIAO TUNG UNIVERSITY, 2007 - 2011
B.S. of Electronics Engineering
Professional Experience
INTEL CORPORATION, 2022 - Present
Physical Design Engineer, Design Service Engineering
- 3DIC testchip execution
- Heterogeneous integration flow enablement
TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD., 2019 - 2022
Principal Eningeer, Design Technology Platform
- 6nm HPC segment customer engagement, flow pipeclean, and project on-site field support
- 5/4/3nm HPC segment customer engagement, PPA assessment, and technical support
- 5/4/3nm node EDA enablement and certification program
- 20+ physical implementation flow trainings to customers in 7/6/5/3 nm technologies
GLOBAL UNICHIP CORPORATION, 2013 - 2019
Deputy Technical Manager, Design Service
- 7nm HPC peripheral block implementation (2M inst.; P&R, timing closure, DRC/LVS)
- 7nm GPU block implementation (1M inst.; P&R, path-finding, customer field support)
- 7nm physical design flow and DDR IP hardening (P&R, timing closure, DRC/LVS, field support)
- 5+ power integrity analysis projects in 28/16nm technology
- 20+ APR and/or power integrity project support experience in sub-28nm nodes