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4 à 6 ans
6 à 10 ans
10 à 15 ans
Plus de 15 ans
Past
R&D process integration engineer @ UMC2014 ~ 2022
・
Semiconductor Engineer
Plus d'1 an
謝宗殷 (Azure) R&D technical manager Tainan City, Taiwan Graduated with a master's degree in the Electrical Engineering Department from National Yang Ming Chiao Tung University. As a R&D technical manager at UMC about 7.7 years of experience, and process integration engineer at TSMC about 3.8 years of experience. Mainly responsible for: semiconductor process development, product yield improvement and device reliability improvement. Email : [email protected] Phone:Work experience R&D technical manager • UMC JuneMarchnm FiNFET BEoL process development, product yield improvement and
Sans Emploi
・
Ne recherche pas de nouvelles opportunités
Temps plein / Intéressé par le travail à distance
10 à 15 ans
National Yang Ming Chiao Tung University
・
Electrical Engineering & IC design
Sans Emploi
Temps plein / Intéressé par le travail à distance
4 à 6 ans
成功大學
・
微電漿系統
Past
Software developer @Freelance Software Development2019 ~ Présent
・
Dans 1 mois
party software for project 2.Software development and maintenance • iOS app with swift/Objective-C • Multiplatform app (iOS / macOS) with SwiftUI • Windows/Linux application with c++ 3.Software Maintenance • Function expansion • Backward/forward compatible 4.Performance tuning • Identify performance bottlenecks and finetume 5.Framework development • MBaseSDK, a toolkit for iOS app UI development, published on cocoapods 6.Communicate with with PM / UX designer / backend developer • Assist colleagues and provide suggestions • API integration with team Sr SW Engineer • YOLO Future Life Co.LtdProduct for travel 1.
Sans Emploi
・
Prêt à l'interview
Temps plein / Intéressé par le travail à distance
6 à 10 ans
National Cheng Kung University (NCKU), Taiwan 國立成功大學
・
Computer Science and Information EngineeringLe Plan de Recrutement le Plus Efficace et Facile
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Definition of Reputation Credits
Technical Skills
Specialized knowledge and expertise within the profession (e.g. familiar with SEO and use of related tools).
Problem-Solving
Ability to identify, analyze, and prepare solutions to problems.
Adaptability
Ability to navigate unexpected situations; and keep up with shifting priorities, projects, clients, and technology.
Communication
Ability to convey information effectively and is willing to give and receive feedback.
Time Management
Ability to prioritize tasks based on importance; and have them completed within the assigned timeline.
Teamwork
Ability to work cooperatively, communicate effectively, and anticipate each other's demands, resulting in coordinated collective action.
Leadership
Ability to coach, guide, and inspire a team to achieve a shared goal or outcome effectively.
Professional Background
Statut Actuel
Progrès de la Recherche d'Emploi
Professions
Semiconductor Engineering
Fields of Employment
Manufacturing
Expérience Professionnelle
6 à 10 ans expérience professionnelle (2 à 4 ans relevant)
Management
None
Compétences
Langues
English
・
Intermédiaire
Job search preferences
Position Désirée
Type d'emploi
Temps plein
Lieu Désiré
Travail à distance
Intéressé par le travail à distance
Freelance
Oui, je suis actuellement indépendant à temps plein.
Éducation
École
國立成功大學
Spécialisation
材料科學及工程學系
In charge of R&D integration 7 years
Communicate, coordinate and cooperate across companies and departments, good communication skills and stress tolerance with others, and cultivate curiosity to get in touch with new knowledge.
Proactive, focused, efficient, attentive, humble and well understanding are my personality traits.
Employment
RD Process Integration • United Microelectronics Corporation
April, 2015 - Feb, 2022
- Conduct keys lots WAT yield analysis through logical reasoning and verify by SEM/TEM with FA team to find process issue in 14nm Finfet technology development from pre-production to mass-production
- Establish device characteristic procedure and train new colleagues quick hands-on
- Manage lot handle to ensure manufacturing quality in 14nm Finfet and 22nm platform technology
- Design Testkey with tools klayout, laker, UDD(user define device), boolean editor and qualify by DRC,PLC, LVS, XOR deck for process monitor in 14nm/22nm/28nm/40nm/MRAM tapeout
- Establish process flow in Power GaN HEMT by investigating worldwide e.g. iMEC and studying academic research e.g. NYCU, CGU for technical pathfinding
- Construct inline AFM methodology to monitor pGaN step-height for Vth, Ron improvement and inline TLM analysis to distinguish Ron into Rc, resistance of access region, resistance of gate for process stability control
- Lead pGaN, passivation loop and cowork with Wavetech, Unikorn,Episil and modules in Power GaN HEMT development to meet device target
- Self-study in academic program e.g. Semiconductor Physics and Devices, Electronics, Electromagnetics, Microwave Engineerings, Radio Frequency Amplifier Design
Education
National Cheng Kung University
Major in Material Science and Engineering
National Chung Hsing University
Major in Material Science and Engineering
Master degree
2012-2014
Bachelor degree
2008-2012
Standard Skills
- PowerPoint
- Excel
Special Skills
- Laker
- Klayout
- DRC
- LVS
Languages
- Chinese — Proficient
- English — Speaking/ Writing/ Reading: Intermediate
In charge of R&D integration 7 years
Communicate, coordinate and cooperate across companies and departments, good communication skills and stress tolerance with others, and cultivate curiosity to get in touch with new knowledge.
Proactive, focused, efficient, attentive, humble and well understanding are my personality traits.
Employment
RD Process Integration • United Microelectronics Corporation
April, 2015 - Feb, 2022
- Conduct keys lots WAT yield analysis through logical reasoning and verify by SEM/TEM with FA team to find process issue in 14nm Finfet technology development from pre-production to mass-production
- Establish device characteristic procedure and train new colleagues quick hands-on
- Manage lot handle to ensure manufacturing quality in 14nm Finfet and 22nm platform technology
- Design Testkey with tools klayout, laker, UDD(user define device), boolean editor and qualify by DRC,PLC, LVS, XOR deck for process monitor in 14nm/22nm/28nm/40nm/MRAM tapeout
- Establish process flow in Power GaN HEMT by investigating worldwide e.g. iMEC and studying academic research e.g. NYCU, CGU for technical pathfinding
- Construct inline AFM methodology to monitor pGaN step-height for Vth, Ron improvement and inline TLM analysis to distinguish Ron into Rc, resistance of access region, resistance of gate for process stability control
- Lead pGaN, passivation loop and cowork with Wavetech, Unikorn,Episil and modules in Power GaN HEMT development to meet device target
- Self-study in academic program e.g. Semiconductor Physics and Devices, Electronics, Electromagnetics, Microwave Engineerings, Radio Frequency Amplifier Design
Education
National Cheng Kung University
Major in Material Science and Engineering
National Chung Hsing University
Major in Material Science and Engineering
Master degree
2012-2014
Bachelor degree
2008-2012
Standard Skills
- PowerPoint
- Excel
Special Skills
- Laker
- Klayout
- DRC
- LVS
Languages
- Chinese — Proficient
- English — Speaking/ Writing/ Reading: Intermediate