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CakeResume Talent Search

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Taiwan
台灣
Engineering
IT
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Less than 1 year
1-2 years
2-4 years
4-6 years
6-10 years
10-15 years
More than 15 years
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National Central University
國立中央大學
Taiwan
台灣
Full-time
Cadence Allegro
Cadence Concept HDL
Cadence OrCAD
Hardware Development
Hardware Troubleshooting
Lightroom
MATLAB
Photoshop
Python coding for BOM check
Software Engineering
No
Within one year
More than one year
Hardware Engineer
軟體工程師/產品工程師
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Master
2015
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Accton
Inspur Taiwan
Interested in working remotely
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English - Fluent
Spanish - Beginner
English
4-6 years
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Avatar of Cheng Wei Lin.
Avatar of Cheng Wei Lin.
Cheng Wei Lin
軟體工程師/產品工程師
Within one year
have afforded me an in-depth understanding of the industry, its unique challenges, and the critical elements required to deliver high-quality software solutions. Senior Software Engineer Hsinchu City, [email protected] Skills Languages Chinese: Native speaker English: Intermediate Spanish: Begineer Tools C# C++ Verilog HDL Matlab PHP & MySQL LabVIEW Interests Photography Reading Badminton Backpacking Mountaineering Marathon Work Experience Senior Software Engineer , JanPresent SYNTEC TECHNOLOGY CO. LTD. , Hsinchu, Taiwan Develop and maintain the product of Laser cutting machine and Press Break with C# and C++ Design and implement complex
english
c++ and c#
Lightroom
Employed
Full-time / Not interested in working remotely
6-10 years
台灣大學工程科學研究所
・
軟體工程師
Avatar of Min-Yung Wang (Martin).
Offline
Avatar of Min-Yung Wang (Martin).
Offline
Min-Yung Wang (Martin)
Hardware Engineer @Inspur Taiwan
・
2019 ~ Present
Hardware Engineer
More than one year
design. Build design module for a half-width motherboard. Build design module of PCI-E re-timer schematics and re-timer debug and troubleshooting . Developed 25/10GbE high speed Ethernet schematics and layout guide. Have experience of the overarching ODM project. 九月五月 2019 EducationNational Central University Master of PhysicsNational Dong Hwa University Bachelor of Physics Skills Language Cadence OrCAD Cadence Allegro Cadence Concept HDL Word、PowerPoint、Excel、Outlook Hardware Troubleshooting Hardware Development Verilog RTL coding based on Intel Altera CPLD Python coding for BOM check English — Advanced Mandarin — N ative speaker
Cadence OrCAD
Cadence Allegro
Cadence Concept HDL
Interested in working remotely
4-6 years
National Central University
・
Master of Physics
100+

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Definition of Reputation Credits

Technical Skills
Specialized knowledge and expertise within the profession (e.g. familiar with SEO and use of related tools).
Problem-Solving
Ability to identify, analyze, and prepare solutions to problems.
Adaptability
Ability to navigate unexpected situations; and keep up with shifting priorities, projects, clients, and technology.
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More than one year
Avatar of Min-Yung Wang (Martin).
Min-Yung Wang (Martin)
Hardware Engineer
Inspur Taiwan
・
2019 ~ Present
Taiwan
Professional Background
Current status
Job Search Progress
Professions
Hardware Engineer
Fields of Employment
Hardware
Work experience
4-6 years
Management
None
Skills
Cadence OrCAD
Cadence Allegro
Cadence Concept HDL
Word、PowerPoint、Excel、Outlook
Hardware Troubleshooting
Hardware Development
Verilog RTL coding base on Intel Altera CPLD
Python coding for BOM check
Languages
English
・
Fluent
Job search preferences
Positions
Hardware Engineer
Job types
Locations
Remote
Interested in working remotely
Freelance
No
Educations
School
National Central University
Major
Master of Physics
Print

Min-Yung Wang (Martin)

Hardware Engineer

An experienced electrical engineer of 5 + years specialized in x86 architecture circuit design and server system integration. Familiar high speed interface design and PCB layout review. Skilled at coordinating cross-function teams to make the design process more efficient and smooth.

 Taiwan

 

Work Experience 

Hardware Engineer  •  Inspur Taiwan

Developed lntel Whitely platform for 2U general server. Including system card design and system level design from EVT to MP.
Design the Open19 server system with AMD platform. Including motherboard bring up and system schematic design.
Design ODM 2U system with Purley platform system on RFQ and concept stage. Including system card schematic design, layout discussion and review, DFM issue solving, and cable solving.
Support 2U4N system with AMD platform. Including system card design and troubleshooting.

十二月 2019 - 七月 2021

Senior Hardware Engineer  •  Accton

Developed Broadcom platform switch schematics design.
Developed Broadcom high speed PHY module
Developed CPU module for high speed switch with Intel Denverton platform.
CPLD RTL coding is based on Altera CPLD.
Measured high speed Signal Integrity (CAUI4/CAUI/XFI/QSGMII/SGMII) .

五月 2019 - 十二月 2019

Senior Hardware Engineer  •  ASRock Rack

Developed high-density 2U4N system and OCP system with lntel grantley and purley platform schematics design.
Build design module for a half-width motherboard.
Build design module of PCI-E re-timer schematics and re-timer debug and troubleshooting.
Developed 25/10GbE high speed Ethernet schematics and layout guide.
Have experience of the overarching ODM project.

九月 2015 - 五月 2019

Education

2013 - 2015

National Central University

Master of Physics

2009 - 2013

National Dong Hwa University

Bachelor of Physics

Skills

Language

  • Cadence OrCAD
  • Cadence Allegro
  • Cadence Concept HDL
  • Word、PowerPoint、Excel、Outlook
  • Hardware Troubleshooting
  • Hardware Development
  • Verilog RTL coding based on Intel Altera CPLD
  • Python coding for BOM check
  • English — Advanced
  • Mandarin — Native speaker
Resume
Profile
Print

Min-Yung Wang (Martin)

Hardware Engineer

An experienced electrical engineer of 5 + years specialized in x86 architecture circuit design and server system integration. Familiar high speed interface design and PCB layout review. Skilled at coordinating cross-function teams to make the design process more efficient and smooth.

 Taiwan

 

Work Experience 

Hardware Engineer  •  Inspur Taiwan

Developed lntel Whitely platform for 2U general server. Including system card design and system level design from EVT to MP.
Design the Open19 server system with AMD platform. Including motherboard bring up and system schematic design.
Design ODM 2U system with Purley platform system on RFQ and concept stage. Including system card schematic design, layout discussion and review, DFM issue solving, and cable solving.
Support 2U4N system with AMD platform. Including system card design and troubleshooting.

十二月 2019 - 七月 2021

Senior Hardware Engineer  •  Accton

Developed Broadcom platform switch schematics design.
Developed Broadcom high speed PHY module
Developed CPU module for high speed switch with Intel Denverton platform.
CPLD RTL coding is based on Altera CPLD.
Measured high speed Signal Integrity (CAUI4/CAUI/XFI/QSGMII/SGMII) .

五月 2019 - 十二月 2019

Senior Hardware Engineer  •  ASRock Rack

Developed high-density 2U4N system and OCP system with lntel grantley and purley platform schematics design.
Build design module for a half-width motherboard.
Build design module of PCI-E re-timer schematics and re-timer debug and troubleshooting.
Developed 25/10GbE high speed Ethernet schematics and layout guide.
Have experience of the overarching ODM project.

九月 2015 - 五月 2019

Education

2013 - 2015

National Central University

Master of Physics

2009 - 2013

National Dong Hwa University

Bachelor of Physics

Skills

Language

  • Cadence OrCAD
  • Cadence Allegro
  • Cadence Concept HDL
  • Word、PowerPoint、Excel、Outlook
  • Hardware Troubleshooting
  • Hardware Development
  • Verilog RTL coding based on Intel Altera CPLD
  • Python coding for BOM check
  • English — Advanced
  • Mandarin — Native speaker