6 years Digital Designer, mainly focus on FPGA(SNPS HAPS80/100) relative design and integrations.
Supervisor Engineer
城市,TW
+886-963-021-002
[email protected]
Xilinx Vivado
Synplify/ProtoCompiler
Xcelium/VCS
SpyGlass Lint/CDC/Power
Verdi
Git
SVN
RTL Design and Verification with Verilog and SystemVerilog
Build project database and environment with Python and Makefile
Maintain and fix UHS-I Design
Maintain and fix Unipro and MPHY Design
Maintain and develop USB3 Gen1&2 Physical Layer(PCS) Design
Provide FPGA Verification Database and relative tools
Deal with customer issues
In charge of AC-DC (Fly Back) Circuit Design
Develop Assembly / C Firmware on Power Management IC
Deal with Power IC verification and customer issue
Deal with Audio IC verification and customer issue
Research on Customer needs and Market Requirement
Co-work with M31 on FPGA Verification with M31 MPHY Board.
Analyze UniPro/UFS trace and improve performance.
Analyze UHS-I Trace and improve performance.
Build CP/FT test case and verify on chip.
ECO all known fault.
Analyze bugs on chip and provide report and work around method for customer side.
Analyze different Voltage behavior between A0 and A2 version and provide ECO method and FW work around.
Research on UHS-I DDR200 and analyze if SD7.0(PCIe Gen1x1) available on current structure.
Verification on USB 3.2 Phy Test Chip with FPGA platform and help analog team to analyze circuit characteristic.
Modify PCS circuit due the restrict of Virtex-7 platform, and add CDC circuit to improve timing violation by break down CTS.
Implementation for data bus sampling on FPGA(UltraScale+) IO at 250MHz.
Build database and environment for UltraScale+ platform.
Provide method for lane de-skew on USB Link Layer for USB 3.2 feature.
Implement Self-LoopBack Design for USB Physical layer to speed up FT run time and lower PCB BOM cost.
Integration on FPGA and ASIC.
Implement UHS-I Host Controller Design & Verification
Implement JTAG Host Controller Design & Verification
Integrate 8051 with UHS-I and JTAG Circuit
Research on choosing FPGA/CPLD for the loader
Analyze Xilinx BitStream JTAG Protocol and provide FW Flow Chart
6 years Digital Designer, mainly focus on FPGA(SNPS HAPS80/100) relative design and integrations.
Supervisor Engineer
城市,TW
+886-963-021-002
[email protected]
Xilinx Vivado
Synplify/ProtoCompiler
Xcelium/VCS
SpyGlass Lint/CDC/Power
Verdi
Git
SVN
RTL Design and Verification with Verilog and SystemVerilog
Build project database and environment with Python and Makefile
Maintain and fix UHS-I Design
Maintain and fix Unipro and MPHY Design
Maintain and develop USB3 Gen1&2 Physical Layer(PCS) Design
Provide FPGA Verification Database and relative tools
Deal with customer issues
In charge of AC-DC (Fly Back) Circuit Design
Develop Assembly / C Firmware on Power Management IC
Deal with Power IC verification and customer issue
Deal with Audio IC verification and customer issue
Research on Customer needs and Market Requirement
Co-work with M31 on FPGA Verification with M31 MPHY Board.
Analyze UniPro/UFS trace and improve performance.
Analyze UHS-I Trace and improve performance.
Build CP/FT test case and verify on chip.
ECO all known fault.
Analyze bugs on chip and provide report and work around method for customer side.
Analyze different Voltage behavior between A0 and A2 version and provide ECO method and FW work around.
Research on UHS-I DDR200 and analyze if SD7.0(PCIe Gen1x1) available on current structure.
Verification on USB 3.2 Phy Test Chip with FPGA platform and help analog team to analyze circuit characteristic.
Modify PCS circuit due the restrict of Virtex-7 platform, and add CDC circuit to improve timing violation by break down CTS.
Implementation for data bus sampling on FPGA(UltraScale+) IO at 250MHz.
Build database and environment for UltraScale+ platform.
Provide method for lane de-skew on USB Link Layer for USB 3.2 feature.
Implement Self-LoopBack Design for USB Physical layer to speed up FT run time and lower PCB BOM cost.
Integration on FPGA and ASIC.
Implement UHS-I Host Controller Design & Verification
Implement JTAG Host Controller Design & Verification
Integrate 8051 with UHS-I and JTAG Circuit
Research on choosing FPGA/CPLD for the loader
Analyze Xilinx BitStream JTAG Protocol and provide FW Flow Chart