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Hsinchu City, Taiwan
Taiwan
IT
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Feng Chia University
逢甲大學
Hsinchu City, Taiwan
Taiwan
Full-time
Debugging
Makefile
PYTHON
Perl
Power Management: Low power verification
Systemverilog
TCL
UPF
Verilog
Xilinx FPGA
No
Within one month
資深數位工程師
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Anpec Electronics Corporation
JMicron Technology Corporation
Silicon Motion
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Avatar of 劉柏頡.
Offline
Avatar of 劉柏頡.
Offline
劉柏頡
主任工程師 @Silicon Motion
・
2020 ~ Present
資深數位工程師
Within one month
劉柏頡 6 years Digital Designer, mainly focus on FPGA(SNPS HAPS80/100) relative design and integrations. Familiar with Simulator(VCS/Xcelium) and FPGA Synthesis tools(SNPS Synplify & ProtoCompiler, Xilinx Vivado). Experienced in script languages, such as Makefile, TCL, Perl and Python. Experienced with EDA tools, such as SNPS SpyGlass and CDNS LEC. Experienced in building some automatic flows using Jenkins and Git. Supervisor Engineer 城市，[email protected] Skills Language SystemVerilog & Verilog C/C++ Python Makefile Perl TCL Tool Xilinx Vivado Synplify/ProtoCompiler Xcelium
SystemVerilog
Xilinx FPGA
Debugging
Employed
・
Ready to interview
Full-time / Interested in working remotely
6-10 years
逢甲大學
・
電子工程
1,000+

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Within two months
Avatar of 劉柏頡.
劉柏頡
主任工程師
Logo of Silicon Motion.
Silicon Motion
・
2020 ~ Present
台灣新竹市
Professional Background
Current status
Employed
Job Search Progress
Ready to interview
Professions
Digital IC Design
Fields of Employment
Semiconductor
Work experience
6-10 years
Management
None
Skills
SystemVerilog
Xilinx FPGA
Debugging
Verilog
Python
Perl
Power Management: Low power verification
UPF
TCL
Makefile
Languages
Chinese
・
Native or Bilingual
English
・
Intermediate
Job search preferences
Positions
資深數位工程師
Job types
Full-time
Locations
Remote
Interested in working remotely
Freelance
Educations
School
逢甲大學
Major
電子工程
Print
Jummcebelas0osnyxmdw

劉柏頡

6 years Digital Designer, mainly focus on FPGA(SNPS HAPS80/100) relative design and integrations. 

  • Familiar with Simulator(VCS/Xcelium) and FPGA Synthesis tools(SNPS Synplify & ProtoCompiler, Xilinx Vivado).
  • Experienced in  script languages, such as Makefile, TCL, Perl and Python.
  • Experienced with EDA tools, such as SNPS SpyGlass and CDNS LEC.
  • Experienced in building some automatic flows using Jenkins and Git.  

Supervisor Engineer 
城市，TW

+886-963-021-002
[email protected]

Skills

Language

SystemVerilog & Verilog
C/C++
Python
Makefile
Perl
TCL


Tool

Xilinx Vivado

Synplify/ProtoCompiler

Xcelium/VCS

SpyGlass Lint/CDC/Power

Verdi

Git

SVN


Working Experience

SMI, Digital Design Senior Engineer , Jul 2020 ~ Now

  • ASIC/FPGA RTL integration
  • FPGA implementation on HAPS-80/100, including STA, Partition and ECO. 
  • Automatic Flow Implementation 

    • SpyGlass Lint/CDC/Power with Jenkins
    • FPGA Daily Synthesis(HAPS80/100) with crontab
    • Git hooks scripts 
  • Genus Synthesis Trail Run
  • UPF modification for ProtoCompiler UC2 flow
  • Build Simulation Environment for ASIC and FPGA 
  • Co-work with FW team on FPGA issues 

JMicron, Digital Design Senior Engineer , Sep 2017 ~ Jul 2020

RTL Design and Verification with Verilog and SystemVerilog
Build project database and environment with Python and Makefile
Maintain and fix UHS-I Design
Maintain and fix Unipro and MPHY Design
Maintain and develop USB3 Gen1&2 Physical Layer(PCS) Design
Provide FPGA Verification Database and relative tools 
Deal with customer issues

Lyra semiconductor Inc. 芯籟半導體股份有限公司, Design Verification Engineer ,Jan 2017 ~ Sep 2017

Develop USBPD RTL Design & Verification
Develop Samsung AFC, Huawei SCP & QC3.0 Controller RTL Design & Verification

Holtek Semiconductor Inc. 盛群半導體股份有限公司, Application Engineer, Oct 2016 ~ Jan 2017

In charge of AC-DC (Fly Back) Circuit Design

Develop Assembly / C Firmware on Power Management IC

ANPEC Electronics Corporation. 茂達電子股份有限公司, Technical Marketing Engineer, Jun 2015 ~ Oct 2016

Deal with Power IC verification and customer issue
Deal with Audio IC verification and customer issue

Research on Customer needs and Market Requirement 

Projects@SMI

Project SM2504

  • Build Lint Checker with Git hook scripts, which will automatically execute Spyglass Lint when detecting changes in files.
  • Build FPGA(HAPS-100) Daily Automatic Synthesis Environment with crontab. 

Project SM2268XT2 

  • Build FPGA(HAPS-100) Daily Automatic Synthesis Environment with crontab. 
  • Build HAPS-100 MDM(Multi-Design Mode) Linux Environment, co-work with IT department.
  • Build LAB environment. 

Project SM2508 

  • Build FPGA(HAPS-80) Daily Automatic Synthesis Environment with crontab. 
  • ASIC RTL integration with Emacs and SystemVerilog. 
  • Build Jenkins Environment for SpyGlass Lint/CDC/Power checking. 
  • Add UPF Verification into ProtoCompiler UC2 flow(HAPS80/100). 
  • Build ASIC(RTL/Netlist)/FPGA Simulation Environment, including Low Power Verification (UPF) with Makefile&Perl and integrate with Avery PCIe/NVMe and other Models(DRAM/NAND/SPI etc). 
  • Trail Run on CDNS Genus.

Project SM2282 

  • Co-work with Intel on Optane Controller integration and FPGA relative issues. 
  • Build ProtoCompiler Netlist simulation for debugging. 
  • Build Snapshot(using tcl script) for Simulation(VCS/Xcelium) to accelerate the CPU time. 
  • Build FT test case for Optane Controller. 
  • Analysis Power and Performance for ASIC with Spyglass.

Others

  • Convert TEST MODE document(excel) to Verilog Module(top mux). 
  • Help building UPF file in hierarchy method. 
  • Research on SystemRDL converting to CSR module.

Projects@JMicron

Project JMS901 

Co-work with M31 on FPGA Verification with M31 MPHY Board.
Analyze UniPro/UFS trace and improve performance.
Analyze UHS-I Trace and improve performance.
Build CP/FT test case and verify on chip.
ECO all known fault.

Project JMS580 

Analyze bugs on chip and provide report and work around method for customer side. 

Project JMS583

Analyze different Voltage behavior between A0 and A2 version and provide ECO method and FW work around. 

Project JMS581

Research on UHS-I DDR200 and analyze if SD7.0(PCIe Gen1x1) available on current structure. 

Project JMS586

Verification on USB 3.2 Phy Test Chip with FPGA platform and help analog team to analyze circuit characteristic.

Modify PCS circuit due the restrict of Virtex-7 platform, and add CDC circuit to improve timing violation by break down CTS.

Implementation for data bus sampling on FPGA(UltraScale+) IO at 250MHz.

Build database and environment for UltraScale+ platform.

Provide method for lane de-skew on USB Link Layer for USB 3.2 feature. 

Implement Self-LoopBack Design for USB Physical layer to speed up FT run time and lower PCB BOM cost. 

Integration on FPGA and ASIC.

Xilinx FPGA loading BitStream with JTAG

Implement UHS-I Host Controller Design & Verification

Implement JTAG Host Controller Design & Verification

Integrate 8051 with UHS-I and JTAG Circuit 

Research on choosing FPGA/CPLD for the loader

Analyze Xilinx BitStream JTAG Protocol and provide FW Flow Chart

Education

MA, Electrical Engineering, Feng Chia University 2011 ~ 2013

逢甲大學, 碩士學位, 電子工程, 2011 ~ 2013

BA, Electrical Engineering, Feng Chia University 2005 ~2010

逢甲大學, 學士學位, 電子工程, 2005 ~ 2010


Resume
Profile
Print
Jummcebelas0osnyxmdw

劉柏頡

6 years Digital Designer, mainly focus on FPGA(SNPS HAPS80/100) relative design and integrations. 

  • Familiar with Simulator(VCS/Xcelium) and FPGA Synthesis tools(SNPS Synplify & ProtoCompiler, Xilinx Vivado).
  • Experienced in  script languages, such as Makefile, TCL, Perl and Python.
  • Experienced with EDA tools, such as SNPS SpyGlass and CDNS LEC.
  • Experienced in building some automatic flows using Jenkins and Git.  

Supervisor Engineer 
城市，TW

+886-963-021-002
[email protected]

Skills

Language

SystemVerilog & Verilog
C/C++
Python
Makefile
Perl
TCL


Tool

Xilinx Vivado

Synplify/ProtoCompiler

Xcelium/VCS

SpyGlass Lint/CDC/Power

Verdi

Git

SVN


Working Experience

SMI, Digital Design Senior Engineer , Jul 2020 ~ Now

  • ASIC/FPGA RTL integration
  • FPGA implementation on HAPS-80/100, including STA, Partition and ECO. 
  • Automatic Flow Implementation 

    • SpyGlass Lint/CDC/Power with Jenkins
    • FPGA Daily Synthesis(HAPS80/100) with crontab
    • Git hooks scripts 
  • Genus Synthesis Trail Run
  • UPF modification for ProtoCompiler UC2 flow
  • Build Simulation Environment for ASIC and FPGA 
  • Co-work with FW team on FPGA issues 

JMicron, Digital Design Senior Engineer , Sep 2017 ~ Jul 2020

RTL Design and Verification with Verilog and SystemVerilog
Build project database and environment with Python and Makefile
Maintain and fix UHS-I Design
Maintain and fix Unipro and MPHY Design
Maintain and develop USB3 Gen1&2 Physical Layer(PCS) Design
Provide FPGA Verification Database and relative tools 
Deal with customer issues

Lyra semiconductor Inc. 芯籟半導體股份有限公司, Design Verification Engineer ,Jan 2017 ~ Sep 2017

Develop USBPD RTL Design & Verification
Develop Samsung AFC, Huawei SCP & QC3.0 Controller RTL Design & Verification

Holtek Semiconductor Inc. 盛群半導體股份有限公司, Application Engineer, Oct 2016 ~ Jan 2017

In charge of AC-DC (Fly Back) Circuit Design

Develop Assembly / C Firmware on Power Management IC

ANPEC Electronics Corporation. 茂達電子股份有限公司, Technical Marketing Engineer, Jun 2015 ~ Oct 2016

Deal with Power IC verification and customer issue
Deal with Audio IC verification and customer issue

Research on Customer needs and Market Requirement 

Projects@SMI

Project SM2504

  • Build Lint Checker with Git hook scripts, which will automatically execute Spyglass Lint when detecting changes in files.
  • Build FPGA(HAPS-100) Daily Automatic Synthesis Environment with crontab. 

Project SM2268XT2 

  • Build FPGA(HAPS-100) Daily Automatic Synthesis Environment with crontab. 
  • Build HAPS-100 MDM(Multi-Design Mode) Linux Environment, co-work with IT department.
  • Build LAB environment. 

Project SM2508 

  • Build FPGA(HAPS-80) Daily Automatic Synthesis Environment with crontab. 
  • ASIC RTL integration with Emacs and SystemVerilog. 
  • Build Jenkins Environment for SpyGlass Lint/CDC/Power checking. 
  • Add UPF Verification into ProtoCompiler UC2 flow(HAPS80/100). 
  • Build ASIC(RTL/Netlist)/FPGA Simulation Environment, including Low Power Verification (UPF) with Makefile&Perl and integrate with Avery PCIe/NVMe and other Models(DRAM/NAND/SPI etc). 
  • Trail Run on CDNS Genus.

Project SM2282 

  • Co-work with Intel on Optane Controller integration and FPGA relative issues. 
  • Build ProtoCompiler Netlist simulation for debugging. 
  • Build Snapshot(using tcl script) for Simulation(VCS/Xcelium) to accelerate the CPU time. 
  • Build FT test case for Optane Controller. 
  • Analysis Power and Performance for ASIC with Spyglass.

Others

  • Convert TEST MODE document(excel) to Verilog Module(top mux). 
  • Help building UPF file in hierarchy method. 
  • Research on SystemRDL converting to CSR module.

Projects@JMicron

Project JMS901 

Co-work with M31 on FPGA Verification with M31 MPHY Board.
Analyze UniPro/UFS trace and improve performance.
Analyze UHS-I Trace and improve performance.
Build CP/FT test case and verify on chip.
ECO all known fault.

Project JMS580 

Analyze bugs on chip and provide report and work around method for customer side. 

Project JMS583

Analyze different Voltage behavior between A0 and A2 version and provide ECO method and FW work around. 

Project JMS581

Research on UHS-I DDR200 and analyze if SD7.0(PCIe Gen1x1) available on current structure. 

Project JMS586

Verification on USB 3.2 Phy Test Chip with FPGA platform and help analog team to analyze circuit characteristic.

Modify PCS circuit due the restrict of Virtex-7 platform, and add CDC circuit to improve timing violation by break down CTS.

Implementation for data bus sampling on FPGA(UltraScale+) IO at 250MHz.

Build database and environment for UltraScale+ platform.

Provide method for lane de-skew on USB Link Layer for USB 3.2 feature. 

Implement Self-LoopBack Design for USB Physical layer to speed up FT run time and lower PCB BOM cost. 

Integration on FPGA and ASIC.

Xilinx FPGA loading BitStream with JTAG

Implement UHS-I Host Controller Design & Verification

Implement JTAG Host Controller Design & Verification

Integrate 8051 with UHS-I and JTAG Circuit 

Research on choosing FPGA/CPLD for the loader

Analyze Xilinx BitStream JTAG Protocol and provide FW Flow Chart

Education

MA, Electrical Engineering, Feng Chia University 2011 ~ 2013

逢甲大學, 碩士學位, 電子工程, 2011 ~ 2013

BA, Electrical Engineering, Feng Chia University 2005 ~2010

逢甲大學, 學士學位, 電子工程, 2005 ~ 2010