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Huang Yen Jhih Phone:/ Hsinchu Taiwan / [email protected] Professional Summary Solution-oriented, quick learner, creative and communication skills in dry etching process of semiconductor in 0.13um to 5nm generation. Good analysis ability and logical thinking make less effort and great benefit for issue solution and maintenance. Experience TSMC R&D dry etching process engineer. Sep~ JanN10,N7,N5 etching recipe tuning. Film stack modification, new process development. Clarify issue, verify failure model. Process stability/uniformity improvement, WPH. TSMC dry etching process engineer. Jul~ Augum
Full-time / Interested in working remotely
6-10 years
NCTU
・
Etching process
資深產品工程師 @Dialog Semiconductor 德商戴樂格半導體有限公司台灣分公司2022 ~ Present
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工程師
Within one month
Employed
Full-time / Interested in working remotely
6-10 years
國立交通大學 National Chiao Tung University
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電子工程Unemployed
Full-time / Interested in working remotely
4-6 years
國立台北科技大學
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車輛工程
工程師 @中華映管2004 ~ Present
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工程師
Within one year
來訪稽核，也會陪同應對及解釋，皆有良好應對結果。製程優化實驗： 參與製程優化專案，將Cr製程的BCE站點，經過驗證後，導入相關解決辦法，可提升半導體層BCE的remain穩定度，並且降低BCE殘的發生機率，此案成功導入相關製程，獲得廠內評比前...
Full-time / Interested in working remotely
10-15 years
國立中山大學
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Huang Yen Jhih
Phone: (+886) 975-356-860 / Hsinchu Taiwan / [email protected]
Professional Summary
Solution-oriented, quick learner, creative and communication skills in dry etching process of semiconductor in 0.13um to 5nm generation. Good analysis ability and logical thinking make less effort and great benefit for issue solution and maintenance.
Experience
TSMC R&D dry etching process engineer. Sep. 2014 ~ Jan. 2018
- N10,N7,N5 etching recipe tuning.
- Film stack modification, new process development.
- Clarify issue, verify failure model.
- Process stability/uniformity improvement, WPH.
TSMC dry etching process engineer. Jul. 2010 ~ Aug. 2014
- 0.13um~N40 etching recipe tuning.
- Clarify issue, verify failure model.
- Process stability, WPH, cost down.
Education
- A master's degree of Electrophysics at NTCU, 2008~2010
- A bachelor's degree of physics at NCU, 2002~2006
Patent
Self-aligned double spacer patterning process
Patterning of small line
Metal insulator metal capacitor
Lorem ipsum dolor sit amet, consectetur adipiscing elit. Nam porttitor dapibus ipsum ut efficitur. Aliquam feugiat nec sem dapibus blandit.
Huang Yen Jhih
Phone: (+886) 975-356-860 / Hsinchu Taiwan / [email protected]
Professional Summary
Solution-oriented, quick learner, creative and communication skills in dry etching process of semiconductor in 0.13um to 5nm generation. Good analysis ability and logical thinking make less effort and great benefit for issue solution and maintenance.
Experience
TSMC R&D dry etching process engineer. Sep. 2014 ~ Jan. 2018
- N10,N7,N5 etching recipe tuning.
- Film stack modification, new process development.
- Clarify issue, verify failure model.
- Process stability/uniformity improvement, WPH.
TSMC dry etching process engineer. Jul. 2010 ~ Aug. 2014
- 0.13um~N40 etching recipe tuning.
- Clarify issue, verify failure model.
- Process stability, WPH, cost down.
Education
- A master's degree of Electrophysics at NTCU, 2008~2010
- A bachelor's degree of physics at NCU, 2002~2006
Patent
Self-aligned double spacer patterning process
Patterning of small line
Metal insulator metal capacitor
Lorem ipsum dolor sit amet, consectetur adipiscing elit. Nam porttitor dapibus ipsum ut efficitur. Aliquam feugiat nec sem dapibus blandit.