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TSMC) JulyApril 2014 Process integration engineer from 20nm to 40nm - 55/65nm - 90nm and other mature technologies 1. Mature technology node: Customer handling (including new tape-out, low yield analysis, WAT, SPC chart) 2. Advanced technology node: 20nm process transfer from Hsinchu to Tainan, and 2P2E-DUV pitch 64nm Cu-interconnect process development EducationNational Yang Ming Chiao Tung University Electrical Engineering & IC designChang Gung University，CGU Electrical Engineering Department Personal advantage Strong learning ability Good at teamwork High problem solving ability Skills Reliability improvement Defect reduction Process Integration Yield Enhancement Failure Analysis Language English — Intermediate Japanese — Elementary

software Photoshop, Illustrator, Sketch, Zeplin 善於使用Photoshop, Illustrator, Sketch, Zeplin ░ Illustration/ hand-drawing with Graphic design experience 有 插圖/手繪與平面設計經驗 ░ Establish design guidelines 懂得建立設計規範 ░ Favorite in teamwork 喜歡團隊合作 contact me anytime LOCKER Pick system Transit - Passenger Feedback website Condo Key collections booking system Zoo Park / Incident Management System Red Cross Volunteer Registration Doodle Maru Doodle rope skipping Doodle A set of 40 digital stickers for LINE App Doodle have a

manage a data team of 10 from scratch, responsible for forming strategic data transforming plan for company. 2.Build and design data center for data storage and integration data from different sources. 3.Design team KPI directly with CEO to motivate and quantify the contribution of teamwork. 4.Customize personal growing path for each member and build a sharing and life-long learning team culture. 5.Collaborate with PM and vendor to design the ERP system in order to accelerate operation efficiency. 6.Design and develop automation platform for multiple

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