About the job

The job focuses on the development of tightly/loosely coupled acceleration computing units for specified applications, such as machine learning, a complex task that requires an understanding of software workloads, pain points in implementation, and effective partitioning of the workload between a general-purpose processor and a hardware acceleration. We research, design, and develop new technologies and architecture to make computing faster, seamless, and more efficient.

Responsibilities

• Define the next generation machine learning accelerator architecture and ISA for machine learning applications.
• Explore various trade-offs of future architecture designs in terms of performance, power, energy, and area. Initiate new feature modeling in the architecture simulator.
• Work with compiler engineers to optimize compilation results and extend the compiler infrastructure.
• Work with software engineers to partition machine learning workload to selected compute engines to enhance user experiences.

Minimum qualifications:

• Master degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience
• 3 years of experience in computer or chip architecture, performance, and/or compiler
• Experience with one or more general purpose programming languages, including C/C++ or Python

Preferred qualifications:

• PhD degree in Computer Science or Electrical Engineering
• Experience with domain-specific accelerators
• Experience with distributed/parallel programming
• Experience with hardware/software co-design for machine learning
• Experience with micro-architecture