Timing signoff analysis engineer/technical manager

1 Develop the Timing signoff criterion for leading process node and 3DIC.
2 Maintain the Timing signoff criterion ,provide issue solving and consultant for projects on abnormal/unfixable timing violation
3 Develop new Timing signoff methodology to be applied during chip synthesis/APR/STA.
4 SPICE correlation for new timing signoff criterion
5 Regression test for every signoff methodology by STA violation/slack analysis.
6 Post-silicon data analysis for silicon-proven timing signoff criterion

1 "Knowledge of timing sign-off fundamentals : signal integrity analysis, cross-talk, and OCV (AOCV, POCV) effects, etc. Experience using timing sign-off tools : PrimeTime/Tempus/HSPICE .
Experience in design margin modeling, including CCS/AOCV/POCV/LVF is a plus"
2 Understanding of programming fundamentals and concepts. Proficient programming skills in Python, Tcl , Perl .
3 Ability to collaborate effectively with different teams . Good communication to describe issues accurately to management.
4 Familiar with timing sign-off factors : OCV/IR/thermal/Reliability , and spice simulation. Experience in on-die sensor design is a plus
5 Experience in exploring and defining new process node sign-off criterion : N7/N5/N3/3DIC is a plus
6 Familiarity with gate level design flows, such as PGB , place-and-route, schematic/layout design, RC extraction, physical verification is a plus