1. SOC physical design implementation including floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout etc.
2. Build physical design implementation flow for advanced process nodes including timing/power/DFM closure and CPU/GPU hardening.
3. Project leader and cross team project handling

1. Familiar with ASIC design flow including STA, LEC and DFT is a plus
2. Familiar with physical design flow including hierarchical design and low power design is a plus
3. Familiar with Cadence Innovus & Synopsys ICC2 is a plus
4. Hierarical physical design and advanced process node experiences (N6, N12 and N16) is a plus
5. Project leader and cross team communications experiences is a plus
6. TCL/Perl programming is a plus
7. 4+ years of physical design hands on working experience