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Digital IC Design
Logo of WASAI Technology.
This internship shall last at least 4 months at full-time or 2-4 days per week part-time. Please make sure you will be able to complete this period before sending your application. * Studying and developing RTL code using Verilog to accelerate kernels for Big Data platforms * System debug & Validation of FPGA prototype systems * Performance analysis and tuning of workloads on heterogeneous platform
台灣台北市
200 ~ 500 TWD / hour
No requirement for relevant working experience
No management responsibility
Logo of WASAI Technology.
* Design and develop RTL for Big Data platform. * Defines and documents RTL changes required for emulation/FPGA. * Tests and debugs the emulation/FPGA model and collaterals. * Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. *You will join a growing team of IC design engineering professionals and have a real opportunity to have your hardware solutions embraced and to demonstrate your coaching and mentoring skills
OpenCL
Verilog
VHDL
台灣台北市
80K ~ 200K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of VICI Holdings 威旭資訊有限公司.
VICI Holdings 威旭資訊是一間專注於高頻、造市及套利交易的公司,我們進行量化研究並追求更好的交易策略。擁有領先全台的軟體研發團隊,並具備華爾街等級的FPGA設計技術,據此打造低延遲全自動交
FPGA
Verilog
100台灣台北市中正區
75K ~ 100K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)
IC Designer
Top integrator
SoC
台灣新竹市新竹
1.8M ~ 3M TWD / year
1 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
Design Verification
DV
Systemverilog
Hsinchu, Hsinchu City, Taiwan
4M ~ 5M TWD / year
6 years of experience required
Managing 1-5 staff
Logo of VICI Holdings 威旭資訊有限公司.
VICI Holdings 威旭資訊是一間專注於高頻交易、造市及套利交易的公司,我們進行量化研究並追求更好的交易策略。擁有領先全台的軟體研發團隊,並具備華爾街等級的FPGA設計技術,據此打造低延遲全自
FPGA
Verilog
100台灣台北市中正區
100K ~ 150K TWD / month
5 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
300台灣新竹市東區
2.5M ~ 3.5M TWD / year
5 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
Verify digital designs of large SoCs using advanced verification methodologies such as UVM. Build reusable bus functional models, monitors, checkers and scoreboards with coverage driven methodology. Understand the design and implementation, define the verification scope, develop the verification infrastructure. Write and execute test plan to verify a design in a timely manner.
Design Verification
UVM
SystemVerilog
Zhudong Township, Hsinchu County, Taiwan 310
2M ~ 3M TWD / year
2 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
碩士以上;電機、電機與控制、電信、電子相關科系畢業為主 需具備5年以上相關工作經驗 熟悉C、Verilog及一般IC設計流程,有數位 IC設計經驗或FPGA使用經驗,或通訊網路電路設計開發經驗者為佳 具數
Ethernet Switch
Switch
IC design
Hsinchu, Hsinchu City, Taiwan
2M ~ 3M TWD / year
5 years of experience required
No management responsibility
Logo of CakeResume Headhunting Recruitment Service.
1.Micro-architecture / RTL design, simulation and verification 2.Chip integration, algorithm implementation or interface design. 3.Familiar CDC, synthesis, formality and STA flow 4. Familiar with FPGA integration, synthesis and verification. 5. Familiar with USB/ High-speed IO related project design is a plus
Digital IC Designer
IC design
Memory
Taipei, Taiwan
1.5M ~ 2.5M TWD / year
3 years of experience required
No management responsibility

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