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• 面板驅動IC 或 SoC 設計

VICI Holdings 威旭資訊是一間專注於高頻、造市及套利交易的公司，我們進行量化研究並追求更好的交易策略。擁有領先全台的軟體研發團隊，並具備華爾街等級的FPGA設計技術，據此打造低延遲全自動交

1. ASIC Design or IP Integration 2. Familiar with Digital front-end EDA tool.

This internship shall last at least 4 months at full-time or 2-4 days per week part-time. Please make sure you will be able to complete this period before sending your application. * Studying and developing RTL code using Verilog to accelerate kernels for Big Data platforms * System debug & Validation of FPGA prototype systems * Performance analysis and tuning of workloads on heterogeneous platform

面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)

工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計

We are now looking for a Research Scientist - Circuits - New College Graduate. Advanced circuit design is critically important in the post-Moore’s Law age. Without the ability to scale process to increase performance and reduce power, we must rely more and more on creative architectural and underlying circuit solutions to provide continuing advancement from generation to generation. NVIDIA Research is seeking world-class circuit researchers to contribute to the exploration of future high-perform

VICI Holdings 威旭資訊是一間專注於高頻交易、造市及套利交易的公司，我們進行量化研究並追求更好的交易策略。擁有領先全台的軟體研發團隊，並具備華爾街等級的FPGA設計技術，據此打造低延遲全自

1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to deliver functionally correct design blocks. 5. Close coverage measures to identify verification holes and to sh

1.Micro-architecture / RTL design, simulation and verification 2.Chip integration, algorithm implementation or interface design. 3.Familiar CDC, synthesis, formality and STA flow 4. Familiar with FPGA integration, synthesis and verification. 5. Familiar with USB/ High-speed IO related project design is a plus