This internship shall last at least 4 months at full-time or 2-4 days per week part-time. Please make sure you will be able to complete this period before sending your application.
* Studying and developing RTL code using VHDL or Verilog to accelerator kernels for Big Data platforms
* System debug & Validation of FPGA prototype systems
* Performance analysis and tuning of workloads on heterogeneous platform
1. 具備 Verilog/VHDL/FPGA 設計經驗 2. 對於 startup 有熱誠 3. Strong technical and problem solving skills. 4. Strong written and verbal communications skills. 5. Ability to define and execute tasks with limited direction. 加分條件：有 Hadoop 相關經驗