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http://wasaitech.com
@wasaitech
10846台北市萬華區長沙街二段6...

Verilog/VHDL Design Senior Engineer

Job Description

* Design and develop RTL for Big Data platform. 
* Defines and documents RTL changes required for emulation/FPGA. 
* Tests and debugs the emulation/FPGA model and collaterals.
* Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. 

Requirements

Must Have: * A Bachelors or Masters degree in Electrical Engineering, Computer Engineering or equivalent * A minimum of 2 years of relevant industry experience. * System Verilog/Verilog/VHDL coding experience * Enthusiastic about working at a start-up company Nice to have: * Altera or Xilinx FPGA design background * Real time C/C++ development and debug tools * Extensive synthesis and simulation skills with professional grade tools * Proficient at debug of high speed logic designs using sophisticated test equipment * QPI/PCIe/CAPI/CCIX/Gen-Z knowledge * Knowledge of ASIC design * Knowledge of CPU/GPU/DDR/SAS/SATA technology * Python script development experience * Exposure to revision control systems * Excellent written and verbal communication skills * Big data or Hadoop knowledge

Salary

Monthly TWD 40,000 ~ 150,000

Location

台北

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