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Logo of Jabil Taiwan.
Build your career with Jabil! We challenge and empower you to make most of your talents, working with outstanding colleagues from diverse backgrounds who share your drive and passion to make Jabil grow! JOB SUMMARY Under the guidance of management, develops new engineering design of a basic to moderate complexity. Gathers design requirements and recommends steps to implement basic to moderate reference design. implementation or design modifications of existing product. Perform and analyze basic
Verilog
RTL
FPGA
241台灣新北市三重區
40K+ TWD / month
1 years of experience required
No management responsibility
Logo of Andes Technology 晶心科技.
1. Verify RISC-V SOC platform including bus fabric, peripheral IPs: SPI, UART, I2C, PWM…etc. 2. Build testbench, develop and maintain in-house VIP 3. Create rand constraint conditions, analysis coverage holes and fill them 4. Create function coverage points to make sure all functions are under test
Verilog
C
C++
台灣新竹市新竹
50K ~ 150K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of 台灣電子設計自動化股份有限公司.
TESDA, a fast growing startup is looking for manager with 5+ years experience and 1~5 digital design verification engineers. As a design verification engineer at TESDA, you'll be able to access and verify the design and implementation of hugely complex SoC from world class companies,attractive package and stock options. If you are looking for a position that can offer huge growth opportunity for career and personal finance and work-life balance, TESDA is the
Verilog
SystemVerilog
C/C++
80K ~ 200K TWD / month
5 years of experience required
Managing 5-10 staff
Logo of 智微科技股份有限公司.
1. Verify RTL design with System Verilog and UVM verification methodology. 2. PCIe or USB or SATA related VIP test maintenance and development. 3. Develop verification platform or behavioral models. 4.Test planning, testbench documentation and development.
Verilog
台灣新竹市新竹
60K ~ 80K TWD / month
No management responsibility
Logo of VICI Holdings 威旭資訊有限公司.
VICI Holdings 威旭資訊是一間專注於高頻、造市及套利交易的公司,我們進行量化研究並追求更好的交易策略。擁有領先全台的軟體研發團隊,並具備華爾街等級的FPGA設計技術,據此打造低延遲全自動交
FPGA
Verilog
100台灣台北市中正區
75K ~ 100K TWD / month
No requirement for relevant working experience
No management responsibility
Logo of VICI Holdings 威旭資訊有限公司.
VICI Holdings 威旭資訊是一間專注於高頻交易、造市及套利交易的公司,我們進行量化研究並追求更好的交易策略。擁有領先全台的軟體研發團隊,並具備華爾街等級的FPGA設計技術,據此打造低延遲全自
FPGA
Verilog
100台灣台北市中正區
100K ~ 150K TWD / month
5 years of experience required
No management responsibility
Logo of NOVATEK 聯詠科技.
【產品線描述】 Smart TV Solutions:提供TVSoC、MEMC/FRC及面板相關顯示裝置的控制晶片 ASIC Solutions:提供智能手機、智能電視、電競螢幕及商用顯示等產品各種ASIC解決方案 PD and Gaming Solutions:提供各種商用顯示及電競螢幕的控制
FPGA
Verilog
No. 2, Hsin Ann Rd, East District, Hsinchu City, Taiwan 300
40K ~ 200K TWD / month
3 years of experience required
No management responsibility
Logo of NOVATEK 聯詠科技.
【產品線描述】 Smart TV Solutions:提供TVSoC、MEMC/FRC及面板相關顯示裝置的控制晶片 ASIC Solutions:提供智能手機、智能電視、電競螢幕及商用顯示等產品各種ASIC解決方案 PD and Gaming Solutions:提供各種商用顯示及電競螢幕的控制
FPGA
Verilog
No. 2, Hsin Ann Rd, East District, Hsinchu City, Taiwan 300
40K ~ 200K TWD / month
2 years of experience required
No management responsibility
Logo of NOVATEK 聯詠科技.
【產品線】 5G手機,AR,VR 顯示技術,AI 人機介面的3D觸控顯示技術,整合生物特徵的全面屏顯示技術。 【工作說明】 1.規劃建置DDIC系統數位DV (Design Verification)的UVM架構平台 2.建置驗證Model來優化信號驗證的效
SystemVerilog
Verilog
C
Zhubei City, Hsinchu County, Taiwan 302
40K ~ 200K TWD / month
3 years of experience required
No management responsibility
Logo of NOVATEK 聯詠科技.
【產品線】 5G手機,AR,VR 顯示技術,AI 人機介面的3D觸控顯示技術,整合生物特徵的全面屏顯示技術。 【工作說明】 1. 高速介面設計 2. 記憶體控制單元設計 3. 面板時序電路設計 4. 面板顯示優
SystemVerilog
Verilog
Zhubei City, Hsinchu County, Taiwan 302
40K ~ 200K TWD / month
3 years of experience required
No management responsibility

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