This internship shall last at least 4 months at full-time or 2-4 days per week part-time. Please make sure you will be able to complete this period before sending your application. * Studying and developing RTL code using VHDL or Verilog to accelerator kernels for Big Data platforms  * System debug & Validation of FPGA prototype systems * Performance analysis and tuning of workloads on heterogeneous platform...

* Design and develop RTL for Big Data platform.  * Defines and documents RTL changes required for emulation/FPGA.  * Tests and debugs the emulation/FPGA model and collaterals.  * Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform.  *You will join a growing team of IC design engineering professionals  and have a real opportunity to have your hardware solutions embraced and  to demonstrate your coaching and mentoring skills.  *There is enormous potential for you...

工作內容： 1.  FPGA firmware design (VHDL/Verilog) 2.  IP usage and integration . 3.  High Speed interface development. 4.  Digital circuit design and analyze. 5.  Issue analysis and solution. 6.  Research and design for new technology.   ...

工作內容： FPGA firmware design (VHDL/Verilog) IP usage and integration . High Speed interface development. Digital circuit design and analyze. Issue analysis and solution. IP Core algotronix provides Advanced Encryption Standard (AES) IP cores targetted to FPGAs Timing constraint  and Timing Analysis ((Propagation Delay Constraint Inequalities) Research and design for new technology.   ...

Job Statement: The Senior FPGA (Design) Engineer will work at the system architecture level in multiple areas of the system as an expert in one or more significant technology domains and will serve as a technical expert in designing, developing, and testing software for optical transport cards using FPGAs (embedded processors) that carry a variety of data types....

* Design and develop OpenCL/HLS/CUDA algorithms for HPC platform.  * Defines and documents OpenCL/HLS/CUDA algorithms required for emulation/FPGA.  * Tests and debugs the emulation/FPGA model and collaterals.  * Develops improvements to usability by digital circuit validation and debugging of failing tests on the emulation platform.  *You will join a growing team of digital IC design engineering professionals  and have a real opportunity to have your hardware solutions embraced and  to demonstrate your coaching and mentoring skills.  *There...

* Design and develop CUDA/OpenCL/HLS algorithms for HPC platform. * Defines and documents CUDA/OpenCL/HLS algorithms required for emulation/FPGA. * Tests and debugs the emulation/FPGA model and collaterals. * Develops improvements to usability by digital circuit validation and debugging of failing tests on the emulation platform. *You will join a growing team of digital IC design engineering professionals and have a real opportunity to have your hardware solutions embraced andto demonstrate your coaching and mentoring skills. *There is...

驅動器產品開發物件導向軟體設計嵌入式系統軟體設計演算法研究與效能優化驅動器整合問題分析與對策研究...

運動控制性能分析伺服系統性能提升研究電機控制方法研究物理系統建模與模擬分析...

1. 熟悉I2C, UART, SPI, GPIO, PWM, ethernet, HDMI…之應用2. 韌體模組化和應用程式開發3. 擅長C/C++、RTL code (Verilog HDL, VHDL) 等程式語言及測試除錯能力4. 了解 Xilinx FPGA / MPU / MCU 並撰寫相關程式5. 熟悉感測元件的整合應用...

as one of the key IPs in many complex SoC. You'll work closely with analog designers and system architects to independently come up with micro-architecture specification and refine adaptation algorithms. You'll then implement the RTL in System Verilog, define test cases that will deeply verify the design and carry out test creations. Next is to define and build constraints for synthesis and drive for timing closure. In addition to RTL design, you'll need to understand the...