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工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with microprocessor architecture. Preferred qualifications: Master's degree or PhD in Electrical Engineering or Computer Science. Experience with modern pro

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with low-power dynamic and leakage, power estimation, as well as data analytics, and profiling. Experience in flow automation (e.g., Python, C, C++). Pre

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with microprocessor architecture. Experience with logic synthesis techniques to optimize RTL code, performance, power, and design techniques. Preferred qual

1.數位電路設計 2.HDL coding(VHDL / Verilog) 3.電路圖繪製Orcad 4.測試程式撰寫 5.產品量產技術移轉

1. FPGA Development for server or communication applications , including IC design , Verilog coding , Simulation , Timing closure , Debug and Project maintenance. 2. Validate and Debug FPGA on prototype hardware system. 3. Co-work with Hardware and Software engineers in development. 4. Design tools implementation

1.Familiar with RTL design & simulation 2.Familiar with FPGA prototype & emulation 3.Familiar with Verilog coding & ASIC design flow 4.Familiar with Analog and digital co-simulation 5.Familiar with Design documentation 6.Experience in MCU 7.Experience in ADC/DAC is a plus 8.Experience in low poer design flow is a plus 孰悉以下工具: 熟悉 Verilog coding, 與 ASIC design flow 熟悉

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Academic coursework in Computer Architecture or Digital Designs. Experience with C/C++ or Verilog/SystemVerilog. Preferred qualifications: Master's degree or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related field. 3 years of experience in RTL design or verif

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques. Experience with CPU or AI accelerator

測試系統開發/維護能力 1. 硬體電路開發設計：類比電路設計、數位電路設計、電源模組設計 2. 韌體程式開發(FPGA/Verilog)