TESDA, a fast growing startup is looking for manager with 5+ years experience and 1~5 digital design verification engineers. As a design verification engineer at TESDA, you'll be able to access and verify the design and implementation of hugely complex SoC from world class companies,attractive package and stock options. If you are looking for a position that can offer huge growth opportunity for career and personal finance and work-life balance, TESDA is the place to be!

What you are expected to do

Verify digital designs of large SoCs using advanced verification methodologies such as UVM.

Build reusable bus functional models, monitors, checkers and scoreboards with coverage driven methodology.

Understand the design and implementation, define the verification scope, develop the verification infrastructure.

Write and execute test plan to verify a design in a timely manner.

What We are looking for

Bachelors, Masters Degree or Ph.D in Electrical Engineering or Computer Science or Computer Engineering or related majors.

Background or interest in verification at Unit/Sub-system/SOC level and expertise in SystemVerilog.

Experience of random stimulus with functional coverage and assertion-based verification methodologies.

Experience in verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.

At least 2 years of relevant experience, school or industry are OK.

What others can make you an excellent fit

Expertise in bus or interconnect protocols (e.g. AXI, AHB, APB) a big plus.

Background in verifying complex ARM/RISC-V based system, understanding RTL designs, and have experience in modeling of digital circuits a big plus.

SystemVerilog, SystemC, C/C++ programming language experience.

Good debugging and analytical skills.

An open mindset & dream to work in an open and lively environment!